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Masafumi Onouchi
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2010 – 2019
- 2012
- [c4]Kazuo Otsuga, Masafumi Onouchi, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa:
An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor. SoCC 2012: 11-14 - 2011
- [c3]Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa:
A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process. A-SSCC 2011: 37-40 - 2010
- [j2]Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Yoshihiko Yasu, Koichiro Ishibashi:
A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS. IEEE J. Solid State Circuits 45(11): 2312-2320 (2010)
2000 – 2009
- 2009
- [c2]Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno
, Mitaro Namiki, Keiji Kimura, Hironori Kasahara
Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. ICPP 2009: 510-517 - 2008
- [j1]Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. IEEE J. Solid State Circuits 43(4): 902-910 (2008) - 2006
- [c1]Masafumi Onouchi, Tetsuya Yamada, Kimihiro Morikawa, Isamu Mochizuki, Hidetoshi Sekine:
A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation. ASP-DAC 2006: 547-550
Coauthor Index
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