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Masakazu Aoki
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2000 – 2009
- 2008
- [j14]Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda:
Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis. IEICE Trans. Electron. 91-C(4): 647-654 (2008) - 2005
- [j13]Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda:
Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an Lsi Chip. IEICE Trans. Electron. 88-C(5): 788-795 (2005) - [c2]Hiroo Masuda, Shin-ichi Ohkawa, Atsushi Kurokawa, Masakazu Aoki:
Challenge: variability characterization and modeling for 65- to 90-nm processes. CICC 2005: 593-599 - [c1]Hiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki:
Approach for physical design in sub-100 nm era. ISCAS (6) 2005: 5934-5937
1990 – 1999
- 1999
- [j12]Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura:
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. IEEE J. Solid State Circuits 34(8): 1084-1090 (1999) - 1998
- [j11]Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Hidetoshi Iwai, Katsuyuki Sato, Tadashi Tachibana:
Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register. IEEE J. Solid State Circuits 33(2): 253-259 (1998) - 1995
- [j10]Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda:
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. IEEE J. Solid State Circuits 30(11): 1165-1173 (1995) - [j9]Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki:
Low-noise, high-speed data transmission using a ringing-canceling output buffer. IEEE J. Solid State Circuits 30(12): 1569-1574 (1995) - 1994
- [j8]Hitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa:
Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs. IEEE J. Solid State Circuits 29(4): 448-453 (1994) - [j7]Takayulu Kawahara
, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki:
A charge recycle refresh for Gb-scale DRAM's in file applications. IEEE J. Solid State Circuits 29(6): 715-722 (1994) - [j6]Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki:
Subthreshold-current reduction circuits for multi-gigabit DRAM's. IEEE J. Solid State Circuits 29(7): 761-769 (1994) - [j5]Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki:
Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's. IEEE J. Solid State Circuits 29(8): 887-894 (1994) - 1993
- [j4]Takao Watanabe, Katsutaka Kimura, Masakazu Aoki, Takeshi Sakata, Kiyoo Ito:
A single 1.5-V digital chip for a 106 synapse neural network. IEEE Trans. Neural Networks 4(3): 387-393 (1993)
1980 – 1989
- 1989
- [j3]Masakazu Aoki, Shin'ichi Ikenaga, Yoshinobu Nakagome, Masashi Horiguchi, Yasushi Kawase, Yoshifumi Kawamoto, Kiyoo Itoh:
New DRAM noise generation under half-V/sub cc/ precharge and its reduction using a transposed amplifier. IEEE J. Solid State Circuits 24(4): 889-894 (1989) - [j2]Masakazu Aoki, Jun Etoh, Kiyoo Itoh, Shin Kimura, Yoshifumi Kawamoto:
A 1.5-V DRAM for battery-based applications. IEEE J. Solid State Circuits 24(5): 1206-1212 (1989) - 1988
- [j1]Masashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Shin'ichi Ikenaga, Katsuhiro Shimohigashi:
An experimental large-capacity semiconductor file memory using 16-levels/cell storage. IEEE J. Solid State Circuits 23(1): 27-33 (1988)
Coauthor Index
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