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Katsutaka Kimura
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2000 – 2009
- 2002
- [j9]Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura:
A low-impedance open-bitline array for multigigabit DRAM. IEEE J. Solid State Circuits 37(4): 487-498 (2002) - 2001
- [j8]Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh:
A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. IEEE J. Solid State Circuits 36(11): 1721-1727 (2001)
1990 – 1999
- 1999
- [j7]Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura:
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. IEEE J. Solid State Circuits 34(8): 1084-1090 (1999) - 1998
- [j6]Takayuki Kawahara
, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, Katsutaka Kimura:
20-Mb/s erase/record flash memory by asymmetrical operation. IEEE J. Solid State Circuits 33(1): 119-125 (1998) - [j5]Takayuki Kawahara
Internal voltage generator for low voltage, quarter-micrometer flash memories. IEEE J. Solid State Circuits 33(1): 126-132 (1998) - 1997
- [j4]Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya:
The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory. IEEE J. Solid State Circuits 32(5): 655-661 (1997) - 1996
- [j3]Takayuki Kawahara
Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories. IEEE J. Solid State Circuits 31(11): 1590-1600 (1996) - 1995
- [j2]Takayuki Kawahara
High reliability electron-ejection method for high density flash memories. IEEE J. Solid State Circuits 30(12): 1554-1562 (1995) - 1993
- [j1]Takao Watanabe, Katsutaka Kimura, Masakazu Aoki, Takeshi Sakata, Kiyoo Ito:
A single 1.5-V digital chip for a 106 synapse neural network. IEEE Trans. Neural Networks 4(3): 387-393 (1993)
Coauthor Index
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