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James H. Aylor
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2020 – today
- 2024
- [j30]Xugui Zhou
, Bulbul Ahmed, James H. Aylor, Philip Asare, Homa Alemzadeh
Hybrid Knowledge and Data Driven Synthesis of Runtime Monitors for Cyber-Physical Systems. IEEE Trans. Dependable Secur. Comput. 21(1): 12-30 (2024) - 2021
- [c24]Xugui Zhou, Bulbul Ahmed, James H. Aylor, Philip Asare, Homa Alemzadeh
Data-driven Design of Context-aware Monitors for Hazard Prediction in Artificial Pancreas Systems. DSN 2021: 484-496 - [i1]Xugui Zhou, Bulbul Ahmed, James H. Aylor, Philip Asare, Homa Alemzadeh:
Data-driven Design of Context-aware Monitors for Hazard Prediction in Artificial Pancreas Systems. CoRR abs/2104.02545 (2021)
2000 – 2009
- 2009
- [j29]Mark A. Hanson, Harry C. Powell Jr., Adam T. Barth, Kyle Ringgenberg, Benton H. Calhoun, James H. Aylor, John C. Lach:
Body Area Sensor Networks: Challenges and Opportunities. Computer 42(1): 58-65 (2009) - 2006
- [j28]Doris L. Carver, Ronald G. Hoelzeman, James H. Aylor, Michael G. Hinchey:
Special Issue Introduction: The IEEE Computer Society's 60th Anniversary. Computer 39(10): 22-25 (2006) - [j27]Zachary D. Buckner, Michael L. Reed, James H. Aylor:
Antialiasing Encoder Interface With Sub-Nyquist Sampling. IEEE Trans. Instrum. Meas. 55(6): 2029-2033 (2006) - 2005
- [j26]Murali K. Nethi, James H. Aylor:
Advances in Modelling and Simulation of Large Parallel/distributed Systems. Parallel Process. Lett. 15(4): 397-406 (2005) - 2004
- [j25]Yong Ma, James H. Aylor:
System Lifetime Optimization for Heterogeneous Sensor Networks with a Hub-Spoke Topology. IEEE Trans. Mob. Comput. 3(3): 286-294 (2004) - 2003
- [j24]Ronald D. Williams, Robert H. Klenke, James H. Aylor:
Teaching computer design using virtual prototyping. IEEE Trans. Educ. 46(2): 296-301 (2003) - [c23]Robert H. Klenke, James H. Aylor:
A Proposed Modeling Environment to Teach Performance Modeling and Hardware/Software Codesign to Senior Undergraduates. MSE 2003: 27-28 - [c22]Jason J. Hein, James H. Aylor, Robert H. Klenke:
Performance-Based System Design Education. MSE 2003: 35-36 - 2002
- [j23]James H. Aylor:
The End of Computing Disciplines as We Know Them? Computer 35(1): 4-5 (2002) - [j22]James H. Aylor:
EIC's Message: It has been a Great Ride! Computer 35(12): 12 (2002) - 2001
- [j21]James H. Aylor:
Can We Work Together? Computer 34(1): 4 (2001) - [j20]James H. Aylor:
Keep on Keepin' on. Computer 34(8): 6-7 (2001) - [j19]Robert H. Klenke, James H. Aylor, Moshe Meyassed, William W. Dungan:
Interfaces for mixed-level simulation with sequential elements. J. Syst. Archit. 47(2): 87-101 (2001) - [j18]Gang Han, Robert H. Klenke, James H. Aylor:
Performance Modeling of Hierarchical Crossbar-Based Multicomputer Systems. IEEE Trans. Computers 50(9): 877-890 (2001) - 2000
- [j17]James H. Aylor:
New Computer Departments Reflect our Changing Industry. Computer 33(3): 4-6 (2000) - [j16]Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle:
Dynamic Access Ordering for Streamed Computations. IEEE Trans. Computers 49(11): 1255-1271 (2000) - [c21]Tianjing Jiang, Robert H. Klenke, James H. Aylor, Gang Han:
System level testability analysis using Petri nets. HLDVT 2000: 112-117
1990 – 1999
- 1999
- [j15]James H. Aylor:
Computer for the 21st Century. Computer 32(1): 4-6 (1999) - [j14]Moshe Meyassed, Robert H. Klenke, James H. Aylor:
Resolving unknown inputs in mixed-level simulation with sequential elements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8): 1151-1164 (1999) - [c20]Sung I. Hong, Sally A. McKee, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, William A. Wulf:
Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory. HPCA 1999: 80-89 - [r1]James H. Aylor, Robert H. Klenke:
Performance Modeling and Analysis in VHDL. The VLSI Handbook 1999 - 1998
- [j13]Sally A. McKee, Robert H. Klenke, Kenneth L. Wright, William A. Wulf, Maximo H. Salinas, James H. Aylor, Alan P. Batson:
Smarter Memory: Improving Bandwidth for Streamed References. Computer 31(7): 54-63 (1998) - [c19]Robert M. McGraw, James H. Aylor, Robert H. Klenke:
A Top-Down Design Environment for Developing Pipelined Datapaths. DAC 1998: 236-241 - 1997
- [c18]Robert H. Klenke, Moshe Meyassed, James H. Aylor, Barry W. Johnson, Ramesh Rao, Anup Ghosh:
An Integrated Design Environment for Performance and Dependability Analysis. DAC 1997: 184-189 - [c17]Robert H. Klenke, James H. Aylor:
An undergraduate advanced computer design course using virtual-prototyping. MSE 1997: 62-63 - 1996
- [j12]Joseph M. Wolf, Lori M. Kaufman, Robert H. Klenke, James H. Aylor, Ronald Waxman:
An analysis of fault partitioned parallel test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5): 517-534 (1996) - [c16]Sally A. McKee, Assaji Aluwihare, Benjamin H. Clark, Robert H. Klenke, Trevor C. Landon, Christopher W. Oliver, Maximo H. Salinas, Adam E. Szymkowiak, Kenneth L. Wright, William A. Wulf, James H. Aylor:
Design and Evaluation of Dynamic Access Ordering Hardware. International Conference on Supercomputing 1996: 125-132 - [c15]Robert H. Klenke, James H. Aylor, Joseph M. Wolf:
An analysis of fault partitioning algorithms for fault partitioned ATPG. VTS 1996: 231-239 - 1995
- [c14]Robert M. McGraw, Moshe Meyassed, Robert H. Klenke, James H. Aylor, Ronald D. Williams:
Refinement of system-level designs using hybrid modeling. ICECCS 1995: 409-416 - 1994
- [j11]Sanjaya Kumar, James H. Aylor, Barry W. Johnson, William A. Wulf:
Object-Oriented Techniques in Hardware Design. Computer 27(6): 64-70 (1994) - [c13]Sally A. McKee, Robert H. Klenke, Andrew J. Schwab, William A. Wulf, Steven A. Moyer, James H. Aylor, Charles Y. Hitchcock:
Experimental Implementation of Dynamic Access Ordering. HICSS (1) 1994: 431-440 - [c12]Sanjay Srinivasan, James H. Aylor:
Digital Circuit Testing on a Network of Workstations. ICPP (3) 1994: 115-118 - 1993
- [j10]Sanjaya Kumar, James H. Aylor, Barry W. Johnson, William A. Wulf:
A Framework for Hardware / Software Codesign. Computer 26(12): 39-45 (1993) - [j9]Maximo H. Salinas, Barry W. Johnson, James H. Aylor:
Implementation-Independent Model of an Instruction Set Architecture in VHDL. IEEE Des. Test Comput. 10(3): 42-54 (1993) - [c11]Robert H. Klenke, Lori M. Kaufman, James H. Aylor, Ronald Waxman, Padmini Narayan:
Workstation Based Parallel Test Generation. ITC 1993: 419-428 - [c10]Robert H. Klenke, Ronald D. Williams, James H. Aylor:
Parallelization methods for circuit partitioning based parallel automatic test pattern generation. VTS 1993: 71-78 - [c9]Sanjay Srinivasan, Gnanasekaran Swaminathan, James H. Aylor, M. Ray Mercer:
Combinational circuit ATPG using binary decision diagrams. VTS 1993: 251-258 - 1992
- [j8]Robert H. Klenke, Ronald D. Williams, James H. Aylor:
Parallel-Processing Techniques for Automatic Test Pattern Generation. Computer 25(1): 71-84 (1992) - [j7]James H. Aylor, Alfred Thieme, Barry W. Johnson:
A battery state-of-charge indicator for electric wheelchairs. IEEE Trans. Ind. Electron. 39(5): 398-409 (1992) - [c8]James H. Aylor, Raul Camposano, Michael A. Schuette, Wayne H. Wolf, Nam Sung Woo:
The Future of Embedded System Design. ICCD 1992: 144-146 - [c7]Richard MacDonald, Sanjay Srinivasan, Ronald D. Williams, James H. Aylor:
A novel VHDL-based computer architecture design methodology. RSP 1992: 292-300 - 1991
- [j6]James H. Aylor, Roy L. Russo, Bruce D. Shriver:
The Promise of the Next Decade (Guest Editors' Introduction). Computer 24(9): 15-16 (1991) - [c6]Maximo H. Salinas, Barry W. Johnson, James H. Aylor:
Implementation-Independent Model of an Instruction Set Architecture Using VHDL. ICCD 1991: 140-145 - 1990
- [c5]Gnanasekaran Swaminathan, James H. Aylor, Barry W. Johnson:
Concurrent testing of VLSI circuits using conservative logic. ICCD 1990: 60-65 - [c4]James H. Aylor, James P. Cohoon, E. L. Feldhousen, Barry W. Johnson:
Compacting randomly generated test sets. ICCD 1990: 153-156
1980 – 1989
- 1989
- [c3]F. T. Hady, James H. Aylor, Ronald D. Williams, Ronald Waxman:
Uninterpreted modeling using the VHSIC hardware description language (VHDL). ICCAD 1989: 172-175 - 1988
- [j5]Barry W. Johnson, James H. Aylor, Haytham H. Hana:
Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder. IEEE J. Solid State Circuits 23(1): 208-215 (1988) - [c2]Barry W. Johnson, James H. Aylor:
Reliability and safety analysis in medical applications of computer technology. CBMS 1988: 96-100 - [c1]Ronald Waxman, James H. Aylor, Erich Marschner:
The VHSIC Hardware Description Language (IEEE Standard 1076): Language Features Revisited. COMPCON 1988: 310-315 - 1986
- [j4]James H. Aylor, Ronald Waxman, Charles Scarratt:
VHDL - Feature Description and Analysis. IEEE Des. Test 3(2): 17-27 (1986) - [j3]James H. Aylor, Barry W. Johnson, Bruce J. Rector:
Structured Design for Testability in Semicustom VLSI. IEEE Micro 6(1): 51-58 (1986) - 1981
- [j2]James H. Aylor, Barry W. Johnson, Robert L. Ramey:
The Impact of Microcomputers on Devices to Aid the Handicapped. Computer 14(1): 35-40 (1981)
1970 – 1979
- 1979
- [j1]Robert L. Ramey, James H. Aylor, Ronald D. Williams:
Microcomputer-Aided Eating for the Severely Handicapped. Computer 12(1): 54-61 (1979)
Coauthor Index
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