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Roger Ferrer
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2020 – today
- 2024
- [c24]Marc Blancafort, Roger Ferrer, Guillaume Houzeaux, Marta Garcia-Gasulla, Filippo Mantovani:
Exploiting long vectors with a CFD code: a co-design show case. IPDPS 2024: 453-464 - [i5]Pablo Vizcaino, Filippo Mantovani, Jesús Labarta, Roger Ferrer:
RAVE: RISC-V Analyzer of Vector Executions, a QEMU tracing plugin. CoRR abs/2409.13639 (2024) - [i4]Marc Blancafort, Roger Ferrer, Guillaume Houzeaux, Marta Garcia-Gasulla, Filippo Mantovani:
Exploiting long vectors with a CFD code: a co-design show case. CoRR abs/2411.00815 (2024) - 2023
- [j7]Pablo Vizcaino
, Filippo Mantovani
Acceleration with long vector architectures: Implementation and evaluation of the FFT kernel on NEC SX-Aurora and RISC-V vector extension. Concurr. Comput. Pract. Exp. 35(20) (2023) - [c23]Muhammad Usman, Sergio Iserte, Roger Ferrer, Antonio J. Peña:
OpenMP Offloading to DPU. CLUSTER Workshops 2023: 64-65 - [c22]Muhammad Usman
DPU Offloading Programming with the OpenMP API. SC Workshops 2023: 884-891 - [c21]Filippo Mantovani, Pablo Vizcaino, Fabio Banchelli, Marta Garcia-Gasulla, Roger Ferrer, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta:
Software Development Vehicles to Enable Extended and Early Co-design: A RISC-V and HPC Case of Study. ISC Workshops 2023: 526-537 - [i3]Filippo Mantovani, Pablo Vizcaino, Fabio Banchelli, Marta Garcia-Gasulla, Roger Ferrer, Giorgos Ieronymakis, Nikos Dimou, Vassilis Papaefstathiou, Jesús Labarta:
Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study. CoRR abs/2306.01797 (2023) - [i2]Federico Rossi, Marco Cococcioni, Roger Ferrer Ibáñez, Jesús Labarta, Filippo Mantovani, Marc Casas, Emanuele Ruffaldi, Sergio Saponara:
Compressed Real Numbers for AI: a case-study using a RISC-V CPU. CoRR abs/2309.07158 (2023) - 2022
- [c20]Raul Torres, Roger Ferrer
A Novel Set of Directives for Multi-device Programming with OpenMP. IPDPS Workshops 2022: 401-410 - 2021
- [c19]Víctor López
An OpenMP Free Agent Threads Implementation. IWOMP 2021: 211-225 - 2020
- [c18]Adrian Munera, Sara Royuela, Roger Ferrer, Raúl Peñacoba Veigas
Static Analysis to Enhance Programmability and Performance in OmpSs-2. ISC Workshops 2020: 19-33
2010 – 2019
- 2018
- [j6]Helena Caminal
Performance and energy effects on task-based parallelized applications - User-directed versus manual vectorization. J. Supercomput. 74(6): 2627-2637 (2018) - [i1]Marta Garcia-Gasulla, Guillaume Houzeaux, Roger Ferrer, Antoni Artigues, Víctor López, Jesús Labarta, Mariano Vázquez:
MPI+X: task-based parallelization and dynamic load balance of finite element assembly. CoRR abs/1805.03949 (2018) - 2015
- [c17]Sara Royuela
Compiler analysis for OpenMP tasks correctness. Conf. Computing Frontiers 2015: 7:1-7:8 - [c16]Diego Caballero, Sara Royuela
Optimizing Overlapped Memory Accesses in User-directed Vectorization. ICS 2015: 393-404 - [c15]Raul Vidal, Marc Casas
Evaluating the Impact of OpenMP 4.0 Extensions on Relevant Parallel Workloads. IWOMP 2015: 60-72 - 2011
- [j5]Harm Munk, Eduard Ayguadé
ACOTES Project: Advanced Compiler Technologies for Embedded Streaming. Int. J. Parallel Program. 39(3): 397-450 (2011) - [c14]Vladimir Subotic, Roger Ferrer
Quantifying the Potential Task-Based Dataflow Parallelism in MPI Applications. Euro-Par (1) 2011: 39-51 - 2010
- [j4]Eduard Ayguadé
Extending OpenMP to Survive the Heterogeneous Multi-Core Era. Int. J. Parallel Program. 38(5-6): 440-459 (2010) - [c13]Roger Ferrer
Analysis of Task Offloading for Accelerators. HiPEAC 2010: 322-336 - [c12]Alejandro Duran, Roger Ferrer
A Proposal for User-Defined Reductions in OpenMP. IWOMP 2010: 43-55 - [c11]Eduard Ayguadé
An Extension to Improve OpenMP Tasking Control. IWOMP 2010: 56-69 - [c10]Roger Ferrer
Optimizing the Exploitation of Multicore Processors and GPUs with OpenMP and OpenCL. LCPC 2010: 215-229
2000 – 2009
- 2009
- [j3]Alejandro Duran, Roger Ferrer
A Proposal to Extend the OpenMP Tasking Model with Dependent Tasks. Int. J. Parallel Program. 37(3): 292-305 (2009) - [c9]Alejandro Duran, Xavier Teruel
Barcelona OpenMP Tasks Suite: A Set of Benchmarks Targeting the Exploitation of Task Parallelism in OpenMP. ICPP 2009: 124-131 - [c8]Roger Ferrer
Unrolling Loops Containing Task Parallelism. LCPC 2009: 416-423 - [c7]Roger Ferrer
Achieving high memory performance from heterogeneous architectures with the SARC programming model. MEDEA@PACT 2009: 15-21 - 2008
- [j2]Milos Milovanovic
Nebelung: Execution Environment for Transactional OpenMP. Int. J. Parallel Program. 36(3): 326-346 (2008) - [c6]Roger Ferrer
Evaluation of memory performance on the cell BE with the SARC programming model. MEDEA@PACT 2008: 77-84 - 2007
- [j1]Alejandro Duran, Roger Ferrer
A Proposal for Error Handling in OpenMP. Int. J. Parallel Program. 35(4): 393-416 (2007) - [c5]Xavier Teruel
Support for OpenMP tasks in Nanos v4. CASCON 2007: 256-259 - [c4]Milos Milovanovic
Transactional Memory and OpenMP. IWOMP 2007: 37-53 - [c3]Milos Milovanovic, Roger Ferrer
Multithreaded software transactional memory and OpenMP. MEDEA@PACT 2007: 81-88 - 2006
- [c2]Xavier Martorell
Techniques supporting threadprivate in OpenMP. IPDPS 2006 - [c1]Alejandro Duran, Roger Ferrer, Juan José Costa, Marc González, Xavier Martorell, Eduard Ayguadé, Jesús Labarta:
A Proposal for Error Handling in OpenMP. IWOMP 2006: 422-434
Coauthor Index
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