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Hyeong-Cheol Oh
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2010 – 2019
- 2019
- [j11]Se-Min Lim, Jooyoung Park, Hyeong-Cheol Oh:
Low-Cost Method for Recognizing Table Tennis Activity. IEICE Trans. Inf. Syst. 102-D(10): 2051-2054 (2019) - 2018
- [j10]Seongjin Choi, Hyeong-Cheol Oh:
Pipelined Squarer for Unsigned Integers of Up to 12 Bits. IEICE Trans. Inf. Syst. 101-D(3): 795-798 (2018) - [j9]Se-Min Lim, Hyeong-Cheol Oh, Jaein Kim, Juwon Lee, Jooyoung Park:
LSTM-Guided Coaching Assistant for Table Tennis Practice. Sensors 18(12): 4112 (2018) - 2015
- [j8]Yong-Luo Shen, Seokjin Jung, Hyeong-Cheol Oh:
Loeffler DCT accelerator for small portable devices. IEICE Electron. Express 12(13): 20150411 (2015) - [c6]Seung Yeol Baik, Seokjin Jeong, Hyeong-Cheol Oh:
Design of a Loeffler DCT using Xilinx Vivado HLS (Abstract Only). FPGA 2015: 278 - 2013
- [j7]Yong-Luo Shen, Hyeong-Cheol Oh:
Pipelined implementation of AI-based Loeffler DCT. IEICE Electron. Express 10(12): 20130319 (2013) - 2012
- [j6]Sang-Woo Seo, Yong-Luo Shen, Kwan-Young Kim, Hyeong-Cheol Oh:
Handling Edge Lists in 2D Vector Graphics Hardware. J. Circuits Syst. Comput. 21(3) (2012) - 2011
- [j5]Sang-Woo Seo, Yong-Luo Shen, Kwan-Young Kim, Hyeong-Cheol Oh:
Scanline-based rendering of 2D vector graphics. IEICE Electron. Express 8(11): 788-794 (2011) - [j4]Yong-Luo Shen, Seok-Jae Kim, Sang-Woo Seo, Hyun-Goo Lee, Hyeong-Cheol Oh:
Design of an OpenVG Hardware Rendering Engine. IEICE Trans. Inf. Syst. 94-D(12): 2409-2417 (2011) - 2010
- [j3]Taek-Kyu Kim, Jong-Sung Lee, Hyeong-Cheol Oh:
Accelerating Java Interpretation in Low-Cost Embedded Processors. J. Circuits Syst. Comput. 19(6): 1235-1244 (2010) - [c5]Sang-Woo Seo, Yong-Luo Shen, Sang-Chol Lee, Jong-Sung Lee, Hyeong-Cheol Oh:
An Accelerator for Rendering 2D Vector Graphics. CGVR 2010: 88-
2000 – 2009
- 2005
- [c4]Hyun-Gyu Kim, Hyeong-Cheol Oh:
A DSP-Enhanced 32-Bit Embedded Microprocessor. EUC 2005: 17-26 - [c3]Hyun-Gyu Kim, Hyeong-Cheol Oh:
A Low-Power DSP-Enhanced 32-Bit EISC Processor. HiPEAC 2005: 302-316 - 2002
- [c2]Hyun-Gyu Kim, Hyeong-Cheol Oh:
Efficient Hardware Multiplicative Inverters. ICISC 2002: 313-326
1990 – 1999
- 1997
- [j2]Ronald I. Greenberg, Hyeong-Cheol Oh:
Universal Wormhole Routing. IEEE Trans. Parallel Distributed Syst. 8(3): 254-262 (1997) - 1995
- [j1]Ronald I. Greenberg, Hyeong-Cheol Oh:
Packet Routing in Networks with Long Wires. J. Parallel Distributed Comput. 31(2): 153-158 (1995) - 1993
- [c1]Ronald I. Greenberg, Hyeong-Cheol Oh:
Universal Wormhole Routing. SPDP 1993: 56-63
Coauthor Index
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