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Design of an OpenVG Hardware Rendering Engine Yong-Luo SHEN Seok-Jae KIM Sang-Woo SEO Hyun-Goo LEE Hyeong-Cheol OH Publication IEICE TRANSACTIONS on Information and Systems Vol.E94-D No.12 pp.2409-2417 Publication Date: 2011/12/01 Online ISSN: 1745-1361 DOI: 10.1587/transinf.E94.D.2409 Print ISSN: 0916-8532 Type of Manuscript: PAPER Category: Computer System Keyword: OpenVG, 2D vector graphics, hardware rendering engine, Full Text: PDF(1.9MB)>>
Summary: This paper introduces a hardware engine for rendering two-dimensional vector graphics based on the OpenVG standard in portable devices. We focus on two design challenges posed by the rendering engines: the number of vertices to represent the images and the amount of memory usage. Redundant vertices are eliminated using adaptive tessellation, in which the redundancy can be judged using a proposed cost-per-quality measure. A simplified edge-flag rendering algorithm and the scanline-based rendering scheme are adopted to reduce external memory access. The designed rendering engine occupies approximately 173 K gates and can satisfy real-time requirements of many applications when it is implemented using a 0.18 µm, 1.8 V CMOS standard cell library. An FPGA prototype using a system-on-a-chip platform has been developed and tested. | ||||||||||
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