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Qiang Li 0021
Person information
- affiliation: University of Electronic Science and Technology of China, School of Electronic Science and Engineering, Institute of Integrated Circuits and Systems, Chengdu, China
- affiliation (PhD 2007): Nanyang Technological University, School of Electrical and Electronic Engineering, Integrated Systems Research Laboratory, Singapore
- affiliation (1997 - 2001): Huazhong University of Science and Technology, Wuhan, China
Other persons with the same name
- Qiang Li — disambiguation page
- Qiang Li 0001
— Shenzhen Technology University, China (and 2 more)
- Qiang Li 0002 — University of Technology of Compiègne, France
- Qiang Li 0003 — University of New South Wales, Canberra, Australia
- Qiang Li 0004 — Texas A&M University, College Station, TX, USA
- Qiang Li 0005 — University of Nottingham, UK
- Qiang Li 0006 — Georgia Institute of Technology, Atlanta, GA, USA
- Qiang Li 0007
- Qiang Li 0008
- Qiang Li 0009
- Qiang Li 0010
- Qiang Li 0011
- Qiang Li 0012
- Qiang Li 0013
- Qiang Li 0014
- Qiang Li 0015
- Qiang Li 0016
- Qiang Li 0017
- Qiang Li 0018
- Qiang Li 0019
- Qiang Li 0020
- Qiang Li 0022
- Qiang Li 0023
- Qiang Li 0024
- Qiang Li 0025 — University of Virginia, UVA Center for Wireless Health, Charlottesville, VA, USA
- Qiang Li 0026 — Shanghai Jiao Tong University, School of Electronic Information and Electrical Engineering, Shanghai Key Laboratory of Integrated Administration Technologies for Information Security, China
- Qiang Li 0027
- Qiang Li 0028
- Qiang Li 0029
- Qiang Li 0030
- Qiang Li 0031
- Qiang Li 0032
- Qiang Li 0033
- Qiang Li 0034
- Qiang Li 0035
- Qiang Li 0036
- Qiang Li 0037
- Qiang Li 0038
- Qiang Li 0039 (aka: Tom Li 0001, Qiang (Tom) Li) — Broadcom Corporation, Irvine, CA, USA (and 1 more)
- Joshua Qiang Li
- Qiang Li 0041
- Qiang Li 0042
- Qiang Li 0043 — Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China (and 1 more)
- Qiang Li 0044 — Hikvision Research Institute, Hangzhou, China (and 1 more)
- Qiang Li 0045
- Qiang Li 0046
- Qiang Li 0047
- Qiang Li 0048
- Qiang Li 0049
- Qiang Li 0050
- Qiang Li 0051
- Eric Q. Li (aka: Eric Li 0002, Qiang Li 0052) — Intel China Research Center, Beijing, China (and 1 more)
- Qiang Li 0053
- Qiang Li 0054
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2020 – today
- 2024
- [j39]Xiaodan Zhou
A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in 0.18 μm CMOS. Microelectron. J. 146: 106144 (2024) - [j38]Yueduo Liu
A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 515-525 (2024) - [j37]Ruofan Zhang, Haoyu Zhuang
A 20 MHz, 98.7 dB-SFDR, Capacitively Degenerated Dynamic Amplifier Without Bias Voltage Calibrations. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1027-1031 (2024) - [j36]Yirui Cao
A 0.8-V Supply, 1.58% 3σ-Accuracy, 1.9-μW Bandgap Reference in 0.13-μm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1884-1888 (2024) - [j35]Haoyu Zhuang
A 0.5-V Voltage Reference Using Simple Common-Source Amplifier With Improved Gain. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4723-4727 (2024) - [j34]Ercong Yu
Deep Learning Assisted Multiuser MIMO Load Modulated Systems for Enhanced Downlink mmWave Communications. IEEE Trans. Wirel. Commun. 23(7): 6750-6764 (2024) - 2023
- [j33]Ruiqi Guo
TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization. IEEE J. Solid State Circuits 58(3): 852-866 (2023) - [j32]Zehao Zhang, Shiheng Yang
On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 26-30 (2023) - [j31]Yuchen Wei
A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1248-1252 (2023) - [c66]Haoyu Zhuang, Nan Sun, Yirui Cao
A 0.69-Noise-Efficiency-Factor 4 x-Current-Reuse Dynamic Comparator with A Stacking FIA. CICC 2023: 1-2 - [c65]Xingchen Chao, Qiang Li:
A 128-GS/s Timing-Robust Sampling Architecture Exploiting Analog FFT. ISCAS 2023: 1-4 - [c64]Feng Tai, Ziqin Nie, Yinhao Wang, Xingchen Chao, Qiang Li:
A Low-Noise and Settling-Enhanced Switched-Capacitor Amplifier With Correlated Level Shifting and Bandwidth Switching. ISCAS 2023: 1-4 - [c63]Michael Pietzko, Julian Spiess, Jonathan Ungethüm, John G. Kauffman, Qiang Li, Maurits Ortmanns:
Bitwise ELD Compensation under Integrator Nonidealities in ΔΣ Modulators. NEWCAS 2023: 1-5 - [c62]Feng Tai, Qiang Li:
Improved Dynamic Comparator With Adaptive Delay Line for the Latch Conduction and Regenerative Feedback Assisted FIA. NEWCAS 2023: 1-5 - 2022
- [j30]Sanfeng Zhang
A 130-dB CMRR Instrumentation Amplifier With Common-Mode Replication. IEEE J. Solid State Circuits 57(1): 278-289 (2022) - [j29]Pengfei Zhai, Zheng Zhu, Xiong Zhou
An On-Chip Power-Supply Noise Analyzer With Compressed Sensing and Enhanced Quantization. IEEE J. Solid State Circuits 57(1): 302-311 (2022) - [j28]Yueduo Liu
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 495-505 (2022) - [c61]Mingkang Zhang, Zihao Zhu, Yueduo Liu, Zehao Zhang, Rongxin Bao, Jiahui Lin, Haovu Zhuang, Jiaxin Liu, Xiong Zhou, Shiheng Yang, Qiang Li:
A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS. ICTA 2022: 36-37 - [c60]Jing Zhang, Lulu Zhang, Xiong Zhou, Maurits Ortmanns, Qiang Li:
A 13-bit 1-MS/s SAR ADC With Rotation-Based Mismatch Error Cancellation. ISCAS 2022: 6-10 - [c59]Jonathan Ungethüm, Michael Pietzko
Maximizing the Inter-Stage Gain in CT 0-X MASH Delta-Sigma-Modulators. ISCAS 2022: 561-565 - [c58]Michael Pietzko
Bitwise ELD Compensation in Δ∑ Modulators. ISCAS 2022: 566-570 - [c57]Borui Tan, Sanfeng Zhang, Chen Gao, Xiong Zhou, Qiang Li:
A 100dB-TCMRR 8-Channel Bio-Potential Front-End with Multi-Channel Common-Mode Replication. ISCAS 2022: 2584-2588 - [c56]Jingjing Li, Xingchen Chao, Qiang Li:
16- and 64-Point Analog Computing of FFT with Improved Performance and Efficiency. PRIME 2022: 197-200 - 2021
- [j27]Sanfeng Zhang
An AC-Coupled Instrumentation Amplifier Achieving 110-dB CMRR at 50 Hz With Chopped Pseudoresistors and Successive-Approximation-Based Capacitor Trimming. IEEE J. Solid State Circuits 56(1): 277-286 (2021) - [j26]Xin Si
A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. IEEE J. Solid State Circuits 56(9): 2817-2831 (2021) - [j25]Bojun Hu
Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs. IEEE Open J. Circuits Syst. 2: 304-310 (2021) - [j24]Letian Huang
ECDR$^{2}$2: Error Corrector and Detector Relocation Router for Network-on-Chip. IEEE Trans. Computers 70(4): 606-613 (2021) - [j23]Shiheng Yang
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3108-3112 (2021) - [c55]Xiaodan Zhou, Zehao Li, Yujie Wang, Xiong Zhou, Shiheng Yang, Jiaxin Liu, Qiang Li:
A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC. APCCAS 2021: 189-192 - [c54]Yan Zeng, Shiheng Yang, Yueduo Liu, Zehao Li, Wengang Huang, Xiaozong Huang, Xiong Zhou, Jiaxin Liu, Qiang Li:
A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level Calibration. A-SSCC 2021: 1-3 - [c53]Qiang Yu, Xiong Zhou, Kefeng Hu, Zijian Huang, Haiwen Chen, Xin Si, Jinda Yang, Qiang Li:
A 9.08 ENOB 10b 400MS/s Subranging SAR ADC with Subsetted CDAC and PDAS in 40nm CMOS. ESSCIRC 2021: 391-394 - [c52]Bojun Hu, Sanfeng Zhang, Xiong Zhou, Zehao Li, Xiangxin Pan, Zhaoming Ding, Qiang Li:
A Comparator Speed Enhancement Technique for Near- and Sub-Threshold ADCs. ICECS 2021: 1-4 - [c51]Yajuan He, Ziji Zhang, Xiong Zhou, Qiang Li:
Teaching Logic and Sequential Cell Characterization in Digital Integrated Circuits. ICETT 2021: 66-70 - [c50]Yueduo Liu, Zihao Zhu, Rongxin Bao, Shiheng Yang, Jiaxin Liu, Xiong Zhou, Qiang Li:
A Low-Power RC Oscillator with Offset and Path Delay Cancellation. ICTA 2021: 12-13 - [c49]Bojun Hu, Chao Liu, Sanfeng Zhang, Qiang Li:
A Ku-Band SiGe Phased-Array Transceiver with 6-Bit Phase and Attenuation Control. ISCAS 2021: 1-5 - [c48]Bojun Hu, Sanfeng Zhang, Xiong Zhou, Xiangxin Pan, Zhaoming Ding, Qiang Li:
A Sampling Speed Enhancement Technique for Near-Threshold SAR ADCs. ISCAS 2021: 1-4 - [c47]Yuxin Zhang, Sitao Zeng, Zhiguo Zhu, Zhaolong Qin, Chen Wang, Jingjing Li, Sanfeng Zhang, Yajuan He, Chunmeng Dou, Xin Si, Meng-Fan Chang, Qiang Li:
A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning. ISCAS 2021: 1-5 - [c46]Ruiqi Guo
15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization. ISSCC 2021: 242-244 - 2020
- [j22]Xin Si
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. IEEE J. Solid State Circuits 55(1): 189-202 (2020) - [j21]Zheng Zhu, Xiong Zhou
A 14-bit 4-MS/s VCO-Based SAR ADC With Deep Metastability Facilitated Mismatch Calibration. IEEE J. Solid State Circuits 55(6): 1565-1576 (2020) - [j20]Xiaofei Ma
An NMOS Digital LDO With NAND-Based Analog-Assisted Loop in 28-nm CMOS. IEEE Trans. Circuits Syst. 67-I(11): 4041-4052 (2020) - [j19]Yajuan He
A Probabilistic Prediction-Based Fixed-Width Booth Multiplier for Approximate Computing. IEEE Trans. Circuits Syst. 67-I(12): 4794-4803 (2020) - [j18]Xiaofei Ma
A Fully Integrated LDO With 50-mV Dropout for Power Efficiency Optimization. IEEE Trans. Circuits Syst. II Express Briefs 67-II(4): 725-729 (2020) - [c45]Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su
15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. ISSCC 2020: 246-248 - [c44]Sanfeng Zhang
23.7 A 130dB CMRR Instrumentation Amplifier with Common-Mode Replication. ISSCC 2020: 356-358 - [c43]Pengfei Zhai, Xiong Zhou, Yan Cai, Zheng Zhu, Fan Zhang, Qiang Li
25.4 A Scalable 20GHz On-Die Power-Supply Noise Analyzer with Compressed Sensing. ISSCC 2020: 386-388
2010 – 2019
- 2019
- [j17]Zhaoming Ding
A 0.5-1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator. IEEE J. Solid State Circuits 54(4): 968-977 (2019) - [j16]Lishan Lv
Inverter-Based Subthreshold Amplifier Techniques and Their Application in 0.3-V $\Delta\Sigma$ -Modulators. IEEE J. Solid State Circuits 54(5): 1436-1445 (2019) - [j15]Junshi Wang
Efficient Design-for-Test Approach for Networks-on-Chip. IEEE Trans. Computers 68(2): 198-213 (2019) - [j14]Xin Si
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4172-4185 (2019) - [c42]Pengfei Zhai, Xiong Zhou, Yan Cai, Zheng Zhu, Fan Zhang, Zixiao Lin, Qiang Li:
A Multi-Slice VCO-based Quantizer for On-Chip Power Supply Noise Analysis Achieving 0.11 (mV)2/sqrt(MHz) Noise Floor. A-SSCC 2019: 121-122 - [c41]Sheng Chang, Xiong Zhou, Zhaoming Ding, Qiang Li:
A 12-bit 30MS/s SAR ADC with VCO-Based Comparator and Split-and-Recombination Redundancy for Bypass Logic. ISCAS 2019: 1-5 - [c40]Ruoman Yang, Chao Liu, Xiangyu Zhao, Sheng Chang, Xiong Zhou, Qiang Li:
A Loss-Compensated 5-Bit Ka-Band Digital Phase Shifter with Low RMS Phase/Gain Error Over Wide Temperature Ranges. ISCAS 2019: 1-5 - [c39]Junkai Zhan, Letian Huang, Junshi Wang, Masoumeh Ebrahimi, Qiang Li:
Online Path-Based Test Method for Network-on-Chip. ISCAS 2019: 1-5 - [c38]Xin Si
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. ISSCC 2019: 396-398 - 2018
- [j13]Lishan Lv
A 0.4-V Gm-C Proportional-Integrator-Based Continuous-Time ΔΣ Modulator With 50-kHz BW and 74.4-dB SNDR. IEEE J. Solid State Circuits 53(11): 3256-3267 (2018) - [c37]Sanfeng Zhang, Xiong Zhou, Qiang Li:
A Voltage Swing Robust Pseudo-Resistor Structure for Biomedical Front-end Amplifier. APCCAS 2018: 61-64 - [c36]Letian Huang, Shuyu Chen, Qiong Wu, Masoumeh Ebrahimi, Junshi Wang, Shuyan Jiang, Qiang Li:
A lifetime-aware mapping algorithm to extend MTTF of Networks-on-Chip. ASP-DAC 2018: 147-152 - [c35]Shuyan Jiang, Qiong Wu, Shuyu Chen, Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Qiang Li:
Optimizing dynamic mapping techniques for on-line NoC test. ASP-DAC 2018: 227-232 - [c34]Zhaoming Ding, Xiong Zhou, Qiang Li:
Delta-Measurement Low-Power SAR ADC Architecture with Adaptive Threshold-First Switching. ISCAS 2018: 1-4 - [c33]Yan Xing, Ziji Zhang, Yiduan Qian, Qiang Li, Yajuan He:
An Energy-Efficient Approximate DCT for Wireless Capsule Endoscopy Application. ISCAS 2018: 1-4 - [c32]Chikun Yuan, Letian Huang, Junshi Wang, Qiang Li:
Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip. ISCAS 2018: 1-5 - [c31]Ziji Zhang
Optimal Slope Ranking: An Approximate Computing Approach for Circuit Pruning. ISCAS 2018: 1-4 - [c30]Xiaofei Ma, Yan Lu, Rui Paulo Martins
A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS. ISSCC 2018: 306-308 - [c29]Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. ISSCC 2018: 496-498 - [c28]Zhaoming Ding, Xiong Zhou, Qiang Li
A 0.5-1.1V 10B Adaptive Bypassing SAR ADC Utilizing Oscillation Cycle Information of VCO-Based Comparator. VLSI Circuits 2018: 93-94 - [c27]Haiwen Chen, Xiong Zhot, Qiang Yu, Fan Zhang, Qiang Li:
A >3GHz ERBW 1.1GS/S 8B Two-Sten SAR ADC with Recursive-Weight DAC. VLSI Circuits 2018: 97-98 - 2017
- [j12]Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Qiang Li, Guangjun Li, Axel Jantsch
Minimizing the system impact of router faults by means of reconfiguration and adaptive routing. Microprocess. Microsystems 51: 252-263 (2017) - [c26]Qichao He, Xiong Zhou, Qiang Li:
Optimization of the amplifier's input-referred noise for high resolution comparators. ASICON 2017: 395-397 - [c25]Letian Huang, Xinxin Lin, Junshi Wang, Qiang Li:
A low latency fault tolerant transmission mechanism for Network-on-Chip. ISCAS 2017: 1-4 - [c24]Junshi Wang, Letian Huang, Masoumeh Ebrahimi, Qiang Li, Guangjun Li, Axel Jantsch
Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip. ISCAS 2017: 1-4 - 2016
- [j11]Zhaoming Ding, Haiqi Liu, Qiang Li
Phase-error cancellation technique for fast-lock phase-locked loop. IET Circuits Devices Syst. 10(5): 417-422 (2016) - [j10]Junfeng Gao, Guangjun Li, Letian Huang, Qiang Li
An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency. IEEE Trans. Circuits Syst. II Express Briefs 63-II(4): 341-345 (2016) - [c23]Hailiang Yao, Xiong Zhou, Sanfeng Zhang, Qiang Li:
Fast-settling technique under large electrode offset in integrated biopotential amplifiers. BioCAS 2016: 280-283 - [c22]Junshi Wang, Letian Huang, Qiang Li, Guangjun Li, Axel Jantsch
Optimizing the location of ECC protection in network-on-chip. CODES+ISSS 2016: 19:1-19:10 - [c21]Junshi Wang, Yang Huang, Masoumeh Ebrahimi, Letian Huang, Qiang Li, Axel Jantsch
VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping. MES@ISCA 2016: 18-25 - [c20]Xiong Zhou, Qiang Li, Soren Kilsgaard, Farshad Moradi
A wearable ear-EEG recording system based on dry-contact active electrodes. VLSI Circuits 2016: 1-2 - 2015
- [j9]Junfeng Gao, Guangjun Li, Qiang Li:
Central span switching structure for SAR ADC with improved linearity and reduced DAC power. IEICE Electron. Express 12(5): 20150047 (2015) - [j8]Shitong Yuan, Hai Huang, Qilian Liang, Qiang Li:
Energy efficient comparator for successive approximation register ADCs with application to wireless sensor networks. Int. J. Sens. Networks 17(2): 122-129 (2015) - [j7]Xiaoyang Wang, Hai Huang, Qiang Li
Design Considerations of Ultralow-Voltage Self-Calibrated SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs 62-II(4): 337-341 (2015) - [j6]Xiaoyang Wang, Xiong Zhou, Qiang Li
A High-Speed Energy-Efficient Segmented Prequantize and Bypass DAC for SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 756-760 (2015) - [c19]Chao Liu, Qiang Li, Yihu Li, Xiang Li, Haitao Liu, Yong-Zhong Xiong:
An 890 mW stacked power amplifier using SiGe HBTs for X-band multifunctional chips. ESSCIRC 2015: 68-71 - [c18]Lishan Lv, Qiang Li:
300mV 50kHz 75.9dB SNDR CT ΔΣ Modulator with Inverter-based Feedforward OTAs. ISCAS 2015: 313-316 - [c17]Yajuan He, Ziji Zhang
A fast and energy efficient binary-to-pseudo CSD converter. ISCAS 2015: 838-841 - 2014
- [c16]Zhiliang Qiao, Xiong Zhou, Qiang Li
A 250mV 77dB DR 10kHz BW SC ΔΣ Modulator Exploiting Subthreshold OTAs. ESSCIRC 2014: 419-422 - [c15]Xiaoyang Wang, Qiang Li:
A 10-bit 150MS/s SAR ADC with parallel segmented DAC in 65nm CMOS. ISCAS 2014: 309-312 - [c14]Kun Ao, Yajuan He, Liang Li, Yuxin Wang, Qiang Li:
A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy. ISIC 2014: 83-86 - [c13]Yajuan He, Song Wang, Qi Ling, Qiang Li:
A digital calibration technique for multi-bit-per-stage pipelined ADC. ISIC 2014: 492-495 - [c12]Xiaoyang Wang, Xiong Zhou, Qiang Li:
A energy-efficient high speed segmented prequantize and bypass DAC for SAR ADCs. MWSCAS 2014: 97-100 - [c11]Lishan Lv, Qiang Li
A low-power, CT sigma-delta modulator with a 2b/cycle SAR quantizer. MWSCAS 2014: 845-848 - 2013
- [c10]Hai Huang, Kun Ao, Zhiyong Guo, Qiang Li:
A 0.5V rate-resolution scalable SAR ADC with 63.7dB SFDR. ISCAS 2013: 2030-2033 - [c9]Junfeng Gao, Bo Chen, Guangjun Li, Qiang Li:
A 13-bit 200MS/s PIPELINE ADC in 0.13µm CMOS. MWSCAS 2013: 249-252 - [c8]Junfeng Gao, Guangjun Li, Qiang Li:
High performance SAR ADC with offset and noise tolerance. MWSCAS 2013: 257-260 - [c7]Zhiliang Qiao, Xiong Zhou, Qiang Li:
A 0.25V 97.8fJ/c.-s. 86.5dB SNDR SC ΔΣ modulator in 0.13µm CMOS. MWSCAS 2013: 261-264 - [c6]Jingjing Tian, Guangjun Li, Qiang Li:
Hardware-efficient parallel structures for linear-phase FIR digital filter. MWSCAS 2013: 995-998 - [c5]Yajuan He, Bo Chen, Qiang Li:
Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADC. VLSI-SoC 2013: 348-351 - 2012
- [j5]Xin Ming, Qiang Li, Ze-kun Zhou, Bo Zhang
An Ultrafast Adaptively Biased Capacitorless LDO With Dynamic Charging Control. IEEE Trans. Circuits Syst. II Express Briefs 59-II(1): 40-44 (2012) - [c4]Longfei Wei, Jinyue Ji, Haiqi Liu, Qiang Li:
A multi-rate SerDes transceiver for IEEE 1394b applications. APCCAS 2012: 316-319 - [c3]Chuan-Ping Yan, Guangjun Li, Qiang Li:
A fast correlation based background digital calibration for pipelined ADCs. APCCAS 2012: 579-582 - [c2]Xiong Zhou, Qiang Li:
A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS. CICC 2012: 1-4 - [c1]Shan Qing, Guang-Jun Li, Qiang Li:
A fast-convergence and robust digital calibration algorithm for a 14-bit 200-MS/s hybrid pipelined-SAR ADC. MWSCAS 2012: 442-445 - 2011
- [j4]Zhiyong Guo, Y. P. Zhang, Bo Yan, Qiang Li, Guangjun Li, Habib F. Rashvand:
Waveform distortion performance evaluation using practical antennas in deterministic multipath impulse radio channels. IET Commun. 5(6): 835-843 (2011)
2000 – 2009
- 2008
- [j3]Yue-Ping Zhang, Jun Jun Wang, Qiang Li
Antenna-in-Package and Transmit-Receive Switch for Single-Chip Radio Transceivers of Differential Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(11): 3564-3570 (2008) - 2007
- [j2]Qiang Li
CMOS T/R Switch Design: Towards Ultra-Wideband and Higher Frequency. IEEE J. Solid State Circuits 42(3): 563-570 (2007) - 2006
- [j1]Yue-Ping Zhang, Qiang Li
A Differential CMOS T/R Switch for Multistandard Applications. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 782-786 (2006)
Coauthor Index
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