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Wei-Hsing Huang
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2020 – today
- 2024
- [j9]Hung-Hsi Hsu
, Tai-Hao Wen, Wei-Hsing Huang, Win-San Khwa, Yun-Chen Lo
A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme. IEEE J. Solid State Circuits 59(1): 116-127 (2024) - [j8]Jian-Wei Su
8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2304-2308 (2024) - [c8]Tai-Hao Wen, Hung-Hsi Hsu, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsih Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices. ISSCC 2024: 580-582 - [i1]Wei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq Waqar, Tai-Hao Wen, Meng-Fan Chang, Shimeng Yu:
Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference. CoRR abs/2409.11418 (2024) - 2023
- [j7]Jian-Wei Su
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. IEEE J. Solid State Circuits 58(3): 877-892 (2023) - [c7]Wei-Hsing Huang, Tai-Hao Wen, Je-Min Hung, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Hung-Hsi Hsu, Yu-Hsiang Chin, Yu-Chiao Chen, Chuna-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W. ISSCC 2023: 258-259 - 2022
- [j6]Jian-Wei Su
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. IEEE J. Solid State Circuits 57(2): 609-624 (2022) - 2021
- [j5]Xin Si
A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. IEEE J. Solid State Circuits 56(9): 2817-2831 (2021) - 2020
- [j4]Xin Si
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. IEEE J. Solid State Circuits 55(1): 189-202 (2020) - [j3]Yen-Cheng Chiu, Zhixiao Zhang, Jia-Jing Chen, Xin Si
A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors. IEEE J. Solid State Circuits 55(10): 2790-2801 (2020) - [c6]Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu
A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. DAC 2020: 1-6 - [c5]Jian-Wei Su
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. ISSCC 2020: 240-242 - [c4]Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su
15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. ISSCC 2020: 246-248
2010 – 2019
- 2019
- [c3]Zhixiao Zhang, Jia-Jing Chen, Xin Si, Yung-Ning Tu, Jian-Wei Su
A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors. A-SSCC 2019: 217-218 - [c2]Xin Si
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. ISSCC 2019: 396-398
1990 – 1999
- 1998
- [j2]Wei-Hsing Huang, Chin-Long Wey:
Diagnosability analysis of analogue circuits. Int. J. Circuit Theory Appl. 26(5): 439-451 (1998) - [j1]Wei-Hsing Huang, Chin-Long Wey:
ATPRG: an automatic test program generator using HDL-A for fault diagnosis of analog/mixed-signal integrated circuits. IEEE Trans. Instrum. Meas. 47(2): 426-431 (1998) - [c1]Wei-Hsing Huang, Chin-Long Wey:
Test points selection process and diagnosability analysis of analog integrated circuits. ICCD 1998: 582-587
Coauthor Index
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