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Atieh Lotfi
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2020 – today
- 2024
- [c10]Saurabh Hukerikar, Atieh Lotfi, Yanxiang Huang, Jason Campbell, Nirmal R. Saxena:
Optimizing Large-Scale Fault Injection Experiments through Martingale Hypothesis: A Systematic Approach for Reliability Assessment of Safety-Critical Systems. DSN-S 2024: 111-117 - 2022
- [c9]Nirmal R. Saxena, Atieh Lotfi:
Error Model (EM) - A New Way of Doing Fault Simulation. ITC 2022: 324-333
2010 – 2019
- 2019
- [c8]Jeng-Hau Lin, Atieh Lotfi, Vahideh Akhlaghi, Zhuowen Tu, Rajesh K. Gupta:
Accelerating Local Binary Pattern Networks with Software-Programmable FPGAs. DATE 2019: 1112-1117 - [c7]Atieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Paul Racunas, Nirmal R. Saxena, Richard Bramley, Yanxiang Huang:
Resiliency of automotive object detection networks on GPU architectures. ITC 2019: 1-9 - 2018
- [b1]Atieh Lotfi:
Fault-susceptibility Mitigation and Efficient Use of Resources in Programmable Hardware Accelerators. University of California San Diego, USA, 2018 - [c6]Atieh Lotfi, Nirmal R. Saxena, Richard Bramley, Paul Racunas, Philip P. Shirvani:
Low Overhead Tag Error Mitigation for GPU Architectures. DSN 2018: 314-321 - 2017
- [c5]Atieh Lotfi, Rajesh K. Gupta:
RxRE: Throughput Optimization for High-Level Synthesis using Resource-Aware Regularity Extraction (Abstract Only). FPGA 2017: 294 - [c4]Atieh Lotfi, Rajesh K. Gupta:
ReHLS: Resource-Aware Program Transformation Workflow for High-Level Synthesis. ICCD 2017: 533-536 - 2016
- [c3]Atieh Lotfi, Abbas Rahimi, Amir Yazdanbakhsh, Hadi Esmaeilzadeh, Rajesh K. Gupta:
Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration. DATE 2016: 1279-1284 - 2015
- [j2]Atieh Lotfi, Abbas Rahimi
, Luca Benini
Aging-Aware Compilation for GP-GPUs. ACM Trans. Archit. Code Optim. 12(2): 24:1-24:20 (2015) - 2013
- [j1]Mehdi Semsarzadeh
A fine-grain distortion and complexity aware parameter tuning model for the H.264/AVC encoder. Signal Process. Image Commun. 28(5): 441-457 (2013) - 2012
- [c2]Atieh Lotfi, Arash Bayat, Saeed Safari
Architectural vulnerability aware checkpoint placement in a multicore processor. IOLTS 2012: 118-120 - 2011
- [c1]Atieh Lotfi, Parisa Kabiri, Zainalabedin Navabi:
Configurable architecture for memory BIST. EWDTS 2011: 1-5
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last updated on 2024-09-21 01:46 CEST by the dblp team
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