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Ashok Kumar 0001
Person information
- affiliation (PhD 1999): University of Louisiana at Lafayette, LA, USA
Other persons with the same name
- Ashok Kumar — disambiguation page
- Ashok Kumar 0002
— Government Mahila Engineering College Ajmer, India (and 2 more)
- Ashok Kumar 0003
- Ashok Kumar 0004
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2020 – today
- 2024
- [j15]Kasem Khalil
Dynamic Fault Tolerance Approach for Network-on-Chip Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. 14(3): 384-394 (2024) - [c40]Kasem Khalil, Tamador Mohaidat, Mahmoud Darwich, Ashok Kumar, Magdy A. Bayoumi:
Efficient Hardware Implementation of Artificial Neural Networks on FPGA. AICAS 2024: 233-237 - [c39]Kasem Khalil
Efficient Deep Learning Approach for Breast Cancer Detection. COINS 2024: 1-5 - 2023
- [c38]Kasem Khalil
Low-Power Convolutional Neural Network Accelerator on FPGA. AICAS 2023: 1-5 - 2022
- [j14]Kasem Khalil
Reconfigurable Hardware Design Approach for Economic Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 69(12): 5094-5098 (2022) - [j13]Kasem Khalil
Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 30(3): 303-314 (2022) - [c37]Rodrigue Rizk
A Resource-Saving Energy-Efficient Reconfigurable Hardware Accelerator for BERT-based Deep Neural Network Language Models using FFT Multiplication. ISCAS 2022: 1675-1679 - [c36]Dominick Rizk
An Economic Uniqueness-Improved Reliable Reconfigurable RO PUF for IoT Security. ISCAS 2022: 1680-1684 - [c35]Frederic Rizk, Dominick Rizk
A Cost-Efficient Reversible-Based Reconfigurable Ring Oscillator Physical Unclonable Function. ISCAS 2022: 1685-1689 - [c34]Kasem Khalil
Adaptive Hardware Architecture for Neural-Network-on-Chip. MWSCAS 2022: 1-4 - 2021
- [j12]Kasem Khalil
Self-Healing Router Approach for High-Performance Network-on-Chip. IEEE Open J. Circuits Syst. 2: 485-496 (2021) - [c33]Bappaditya Dey
A Reversible-Logic based Architecture for VGGNet. ICECS 2021: 1-4 - [c32]Kasem Khalil
An Efficient Reconfigurable Neural Network on Chip. ICECS 2021: 1-4 - [c31]Kasem Khalil
A Reversible-Logic Based Architecture for Long Short-Term Memory (LSTM) Network. ISCAS 2021: 1-5 - [c30]Kasem Khalil
An Efficient Embryonic Hardware Architecture based on Network-on-Chip. MWSCAS 2021: 449-452 - [c29]Dominick Rizk
An In-Situ Sliding Window Approximate Inner-Product Scheme Based on Parallel Distributed Arithmetic for Ultra-Low Power Fault-Tolerant Applications. MWSCAS 2021: 503-506 - [c28]Rodrigue Rizk
A Hybrid Capsule Network-based Deep Learning Framework for Deciphering Ancient Scripts with Scarce Annotations: A Case Study on Phoenician Epigraphy. MWSCAS 2021: 617-620 - [c27]Kasem Khalil
A Reversible-Logic based Architecture for Convolutional Neural Network (CNN). MWSCAS 2021: 1070-1073 - [c26]Rodrigue Rizk
An Efficient Capsule Network Reconfigurable Hardware Accelerator for Deciphering Ancient Scripts with Scarce Annotations. SoCC 2021: 75-78 - [c25]Dominick Rizk
A Cost-Efficient Reversible-Based Configurable Ring Oscillator Physical Unclonable Function. SoCC 2021: 79-82 - 2020
- [j11]Kasem Khalil
Intelligent Fault-Prediction Assisted Self-Healing for Embryonic Hardware. IEEE Trans. Biomed. Circuits Syst. 14(4): 852-866 (2020) - [j10]Kasem Khalil
Machine Learning-Based Approach for Hardware Faults Prediction. IEEE Trans. Circuits Syst. 67-I(11): 3880-3892 (2020) - [c24]Kasem Khalil
A Novel Design Reversible Logic Based Configurable Fault-Tolerant Embryonic Hardware. ISCAS 2020: 1-5 - [c23]Bappaditya Dey
A Reversible-Logic based Architecture for Artificial Neural Network. MWSCAS 2020: 505-508 - [c22]Kasem Khalil
Architecture of A Novel Low-Cost Hardware Neural Network. MWSCAS 2020: 1060-1063 - [c21]Omar Eldash, Adam Frost, Kasem Khalil
Dynamically Reconfigurable Deep Learning for Efficient Video Processing in Smart IoT Systems. WF-IoT 2020: 1-6
2010 – 2019
- 2019
- [j9]Kasem Khalil
Self-healing hardware systems: A review. Microelectron. J. 93 (2019) - [j8]Kasem Khalil
Economic LSTM Approach for Recurrent Neural Networks. IEEE Trans. Circuits Syst. II Express Briefs 66-II(11): 1885-1889 (2019) - [c20]Khalid A. Alattas, Aminul Islam, Ashok Kumar, Magdy A. Bayoumi:
Unsupervised Ranking of Numerical Observations based on Magnetic Properties and Correlation Coefficient. HICSS 2019: 1-10 - [c19]Rodrigue Rizk
Demystifying Emerging Nonvolatile Memory Technologies: Understanding Advantages, Challenges, Trends, and Novel Applications. ISCAS 2019: 1-5 - [c18]Bappaditya Dey
A Novel Design Gate based Low-Cost Configurable RO PUF using Reversible Logic. MWSCAS 2019: 211-214 - [c17]Kasem Khalil
A Novel Reconfigurable Hardware Architecture of Neural Network. MWSCAS 2019: 618-621 - [c16]Kasem Khalil
Self-Healing Approach for Hardware Neural Network Architecture. MWSCAS 2019: 622-625 - [c15]Kasem Khalil
N2 OC: Neural-Network-on-Chip Architecture. SoCC 2019: 272-277 - [c14]Kasem Khalil
A Speed and Energy Focused Framework for Dynamic Hardware Reconfiguration. SoCC 2019: 388-393 - 2018
- [c13]Kasem Khalil
An Efficient Approach for Neural Network Architecture. ICECS 2018: 745-748 - [c12]Kasem Khalil
Flexible Self-Healing Router for Reliable and High-Performance Network-an-Chips Architecture. SoCC 2018: 152-157 - 2017
- [c11]Ahmed Sammoud, Ashok Kumar, Magdy A. Bayoumi, Tarek A. Elarabi:
Real-time streaming challenges in Internet of Video Things (IoVT). ISCAS 2017: 1-4
2000 – 2009
- 2007
- [j7]Mitun Bhattacharyya, Ashok Kumar, Magdy A. Bayoumi:
A framework for assessing residual energy in wireless sensor network. Int. J. Sens. Networks 2(3/4): 256-272 (2007) - [j6]Ruth Aguilar-Ponce
A network of sensor-based framework for automated visual surveillance. J. Netw. Comput. Appl. 30(3): 1244-1271 (2007) - [c10]Abu Baker, Soumik Ghosh, Ashok Kumar, Magdy A. Bayoumi, Rafic A. Ayoubi:
Design and Realization of Analog Phi-Function for LDPC Decoder. ISCAS 2007: 1661-1664 - [c9]Ruth Aguilar-Ponce
Pixel-Level Image Fusion Scheme based on Linear Algebra. ISCAS 2007: 2658-2661 - 2006
- [j5]Sumeer Goel, Ashok Kumar, Magdy A. Bayoumi:
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style. IEEE Trans. Very Large Scale Integr. Syst. 14(12): 1309-1321 (2006) - [p1]Mitun Bhattacharyya, Ashok Kumar, Magdy A. Bayoumi:
Intelligent Mechanisms for Energy Reduction in Design of Wireless Sensor Networks using Learning Methods. Integrated Intelligent Systems for Engineering Design 2006: 325-344 - 2005
- [j4]Ruth Aguilar-Ponce
Autonomous Decentralized Systems Based Approach to Object Detection in Sensor Clusters. IEICE Trans. Commun. 88-B(12): 4462-4469 (2005) - [j3]Ashok Kumar, Magdy A. Bayoumi:
A Fast Scheduling Algorithm for Low Power Design. J. Circuits Syst. Comput. 14(4): 735-756 (2005) - [j2]Mohamed A. Elgamel, Ashok Kumar, Magdy A. Bayoumi:
Efficient shield insertion for inductive noise reduction in nanometer technologies. IEEE Trans. Very Large Scale Integr. Syst. 13(3): 401-405 (2005) - [c8]Ruth Aguilar-Ponce, Ashok Kumar, J. Luis Tecpanecatl-Xihuitl, Magdy A. Bayoumi:
An Architecture for Automated Scene Understanding. CAMP 2005: 19-24 - [c7]Mahmoud Elassal, Ashok Kumar, Magdy A. Bayoumi:
A systematic framework for high throughput MAP decoder VLSI architectures. ISCAS (1) 2005: 29-32 - [c6]Ashok Kumar, J. Luis Tecpanecatl-Xihuitl
Low complexity decimation filter for multi-standard digital receivers. ISCAS (1) 2005: 552-555 - [c5]Walid Elgharbawy, Pradeep Golconda, Ashok Kumar, Magdy A. Bayoumi:
A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits. ISCAS (5) 2005: 4697-4700 - 2004
- [j1]Ashok Kumar, Magdy A. Bayoumi, Mohamed A. Elgamel:
A methodology for low power scheduling with resources operating at multiple voltages. Integr. 37(1): 29-62 (2004)
1990 – 1999
- 1999
- [c4]Ashok Kumar, Magdy A. Bayoumi:
Novel Formulations for Low-Power Binding of Function Units in High-Level Synthesis. ICCD 1999: 321-324 - [c3]Ashok Kumar, Magdy A. Bayoumi:
Methodologies for binding function units for low power in high level synthesis. ICECS 1999: 907-910 - [c2]Ashok Kumar, Magdy A. Bayoumi, Raghava V. Cherabuddi:
Minimizing switchings of the function units through binding for low power. ISCAS (1) 1999: 66-69 - [c1]Ashok Kumar, Magdy A. Bayoumi:
Multiple voltage-based scheduling methodology for low power in the high level synthesis. ISCAS (1) 1999: 371-374
Coauthor Index
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last updated on 2024-10-23 20:31 CEST by the dblp team
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