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Yanqing Zhang 0002
Person information
- affiliation: NVIDIA Inc., Santa Clara, CA, USA
- affiliation (PhD): University of Virginia, Charlottesville, VA, USA
Other persons with the same name
- Yan-Qing Zhang 0001 (aka: Yanqing Zhang 0001) — Georgia State University, Atlanta, GA, USA (and 2 more)
- Yanqing Zhang 0003
— Scania AB, Södertälje, Sweden (and 2 more)
- Yanqing Zhang 0004 (aka: Yan-Qing Zhang 0004) — Yunnan University, Department of Statistics, Kunming, China
- Yanqing Zhang 0005 — Electronic Engineering Institute, Hefei, China
- Yanqing Zhang 0006
- Yanqing Zhang 0007
- Yanqing Zhang 0008 — Jiyuan Vocational and Technical College, Economics and Management Department, China
- Yanqing Zhang 0009 — Heilongjiang University, School of Computer Science and Technology, Harbin, China
- Yanqing Zhang 0010
- Yanqing Zhang 0011
- Yanqing Zhang 0012 — Harbin Institute of Technology, Laboratory for Space Environment and Physical Sciences, China
- Yanqing Zhang 0013 — Hebei University of Economics and Business, College of Foreign Languages, Shijiazhuang, China
- Yanqing Zhang 0014 — Jilin University, College of Construction Engineering, Changchun, China
- Yanqing Zhang 0015 — South China University of Technology, Guangzhou, China
- Yanqing Zhang 0016 — Zhengzhou University, School of Software, China
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2020 – today
- 2024
- [c23]Yingjie Li, Anthony Agnesina, Yanqing Zhang, Haoxing Ren, Cunxi Yu:
BoolGebra: Attributed Graph-Learning for Boolean Algebraic Manipulation. DATE 2024: 1-2 - [i4]Yingjie Li, Anthony Agnesina, Yanqing Zhang, Haoxing Ren, Cunxi Yu:
BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation. CoRR abs/2401.10753 (2024) - 2023
- [j7]Haoxing Ren
Machine Learning and Algorithms: Let Us Team Up for EDA. IEEE Des. Test 40(1): 70-76 (2023) - [c22]Dian-Lun Lin
GenFuzz: GPU-accelerated Hardware Fuzzing using Genetic Algorithm with Multiple Inputs. DAC 2023: 1-6 - 2022
- [c21]Yanqing Zhang, Haoxing Ren, Akshay Sridharan, Brucek Khailany:
GATSPI: GPU accelerated gate-level simulation for power improvement. DAC 2022: 1231-1236 - [c20]Haoxing Ren, Siddhartha Nath, Yanqing Zhang, Hao Chen, Mingjie Liu:
Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper). ICCAD 2022: 1:1-1:8 - [c19]Dian-Lun Lin
From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus. ICPP 2022: 88:1-88:12 - [c18]Vidya A. Chhabria
XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning. MLCAD 2022: 63-69 - [i3]Yanqing Zhang, Haoxing Ren, Akshay Sridharan, Brucek Khailany:
GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement. CoRR abs/2203.06117 (2022) - 2021
- [j6]Yakun Sophia Shao, Jason Clemons
Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM 64(6): 107-116 (2021) - [c17]Vidya A. Chhabria
MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification. DATE 2021: 1825-1828 - [c16]Ghasem Pasandi, Sreedhar Pratty, David Brown, Yanqing Zhang, Haoxing Ren, Brucek Khailany:
2021 ICCAD CAD Contest Problem C: GPU Accelerated Logic Rewriting. ICCAD 2021: 1-6 - 2020
- [j5]Brian Zimmer
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits 55(4): 920-932 (2020) - [j4]Brucek Khailany, Haoxing Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William J. Dally:
Accelerating Chip Design With Machine Learning. IEEE Micro 40(6): 23-32 (2020) - [c15]Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza:
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. ASP-DAC 2020: 19-25 - [c14]Yanqing Zhang, Haoxing Ren, Brucek Khailany:
GRANNITE: Graph Neural Network Inference for Transferable Power Estimation. DAC 2020: 1-6 - [c13]Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany:
Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk). ICCAD 2020: 70:1-70:4 - [c12]Yanqing Zhang, Haoxing Ren, Brucek Khailany:
Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk). ICCAD 2020: 166:1-166:5 - [i2]Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza:
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. CoRR abs/2011.13493 (2020) - [i1]Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar:
MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification. CoRR abs/2012.10597 (2020)
2010 – 2019
- 2019
- [c11]Yuan Zhou, Haoxing Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang
PRIMAL: Power Inference using Machine Learning. DAC 2019: 39 - [c10]Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons
A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium 2019: 1-24 - [c9]Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang
MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD 2019: 1-8 - [c8]Yakun Sophia Shao, Jason Clemons
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO 2019: 14-27 - [c7]Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits 2019: 300- - 2018
- [c6]Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons
A modular digital VLSI flow for high-productivity SoC design. DAC 2018: 72:1-72:6 - 2015
- [c5]Alicia Klinefelter, Nathan E. Roberts, Yousef Shakhsheer, Patricia González, Aatmesh Shrivastava, Abhishek Roy, Kyle Craig, Muhammad Faisal, James Boley, Seunghyun Oh, Yanqing Zhang, Divya Akella, David D. Wentzloff, Benton H. Calhoun:
21.3 A 6.45μW self-powered IoT SoC with integrated energy-harvesting power management and ULP asymmetric radios. ISSCC 2015: 1-3 - 2014
- [c4]Yanqing Zhang, Benton H. Calhoun:
Fast, accurate variation-aware path timing computation for sub-threshold circuits. ISQED 2014: 243-248 - 2013
- [j3]Yanqing Zhang, Fan Zhang, Yousef Shakhsheer, Jason Silver, Alicia Klinefelter, Manohar Nagaraju, James Boley, Jagdish Nayayan Pandey, Aatmesh Shrivastava, Eric J. Carlson, Austin Wood, Benton H. Calhoun, Brian P. Otis:
A Batteryless 19 µW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications. IEEE J. Solid State Circuits 48(1): 199-213 (2013) - 2012
- [j2]Benton H. Calhoun, John C. Lach, John A. Stankovic, David D. Wentzloff, Kamin Whitehouse, Adam T. Barth, Jonathan K. Brown, Qiang Li, Seunghyun Oh, Nathan E. Roberts, Yanqing Zhang:
Body Sensor Networks: A Holistic Approach From Silicon to Users. Proc. IEEE 100(1): 91-106 (2012) - [j1]Alicia Klinefelter, Yanqing Zhang, Brian P. Otis, Benton H. Calhoun:
A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 937-941 (2012) - [c3]Yousef Shakhsheer, Yanqing Zhang, Brian P. Otis, Benton H. Calhoun:
A custom processor for node and power management of a battery-less body sensor node in 130nm CMOS. CICC 2012: 1-4 - [c2]Fan Zhang, Yanqing Zhang, Jason Silver, Yousef Shakhsheer, Manohar Nagaraju, Alicia Klinefelter, Jagdish Nayayan Pandey, James Boley, Eric J. Carlson, Aatmesh Shrivastava, Brian P. Otis, Benton H. Calhoun:
A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC. ISSCC 2012: 298-300 - 2010
- [c1]Benton H. Calhoun, Sudhanshu Khanna, Yanqing Zhang, Joseph F. Ryan, Brian P. Otis:
System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms. ISCAS 2010: 269-272
Coauthor Index
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