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Michael Pellauer
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2020 – today
- 2024
- [c39]Nandeeka Nayak
, Toluwanimi O. Odemuyiwa
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators (Abstract). HOPC@SPAA 2024 - [c38]Chakshu Moar, Faraz Tahmasebi, Michael Pellauer, Hyoukjun Kwon:
Characterizing the Accuracy-Efficiency Trade-off of Low-rank Decomposition in Language Models. IISWC 2024: 194-209 - [c37]Nandeeka Nayak, Xinrui Wu, Toluwanimi O. Odemuyiwa, Michael Pellauer, Joel S. Emer, Christopher W. Fletcher:
FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design. MICRO 2024: 1458-1473 - [i13]Chakshu Moar, Michael Pellauer, Hyoukjun Kwon:
Characterizing the Accuracy - Efficiency Trade-off of Low-rank Decomposition in Language Models. CoRR abs/2405.06626 (2024) - [i12]Nandeeka Nayak, Xinrui Wu, Toluwanimi O. Odemuyiwa, Michael Pellauer, Joel S. Emer, Christopher W. Fletcher:
FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design. CoRR abs/2406.10491 (2024) - 2023
- [j10]Michael Pellauer
Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing. ACM Trans. Comput. Syst. 41: 4:1-4:30 (2023) - [c36]Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher:
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling. ASPLOS (3) 2023: 18-32 - [c35]Francisco Muñoz-Martínez, Raveesh Garg
Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing. ASPLOS (3) 2023: 252-265 - [c34]Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer:
Optimizing Compression Schemes for Parallel Sparse Tensor Algebra. DCC 2023: 373 - [c33]Toluwanimi O. Odemuyiwa
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling (Extended Abstract). HOPC@SPAA 2023: 15-16 - [c32]Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer:
Optimizing Compression Schemes for Parallel Sparse Tensor Algebra. HPEC 2023: 1-7 - [c31]Nandeeka Nayak
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators. MICRO 2023: 1255-1270 - [i11]Francisco Muñoz-Martínez, Raveesh Garg
Flexagon: A Multi-Dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing. CoRR abs/2301.10852 (2023) - [i10]Raveesh Garg
Exploiting Inter-Operation Data Reuse in Scientific Applications using GOGETA. CoRR abs/2303.11499 (2023) - [i9]Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer:
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators. CoRR abs/2304.07931 (2023) - 2022
- [j9]Sheng-Chun Kao, Hyoukjun Kwon
A Formalism of DNN Accelerator Flexibility. Proc. ACM Meas. Anal. Comput. Syst. 6(2): 41:1-41:23 (2022) - [j8]Prasanth Chatarasi, Hyoukjun Kwon
Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators. ACM Trans. Archit. Code Optim. 19(1): 6:1-6:26 (2022) - [c30]Ananda Samajdar, Eric Qin, Michael Pellauer, Tushar Krishna:
Self adaptive reconfigurable arrays (SARA): learning flexible GEMM accelerator configuration and mapping-space using ML. DAC 2022: 583-588 - [c29]Sheng-Chun Kao, Michael Pellauer, Angshuman Parashar, Tushar Krishna:
DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators. DATE 2022: 232-237 - [c28]Sheng-Chun Kao, Hyoukjun Kwon
A Formalism of DNN Accelerator Flexibility. SIGMETRICS (Abstracts) 2022: 53-54 - [i8]Eric Qin, Raveesh Garg, Abhimanyu Bambhaniya, Michael Pellauer, Angshuman Parashar, Sivasankaran Rajamanickam, Cong Hao, Tushar Krishna:
Enabling Flexibility for Sparse Tensor Acceleration via Heterogeneity. CoRR abs/2201.08916 (2022) - [i7]Sheng-Chun Kao, Michael Pellauer, Angshuman Parashar, Tushar Krishna:
DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators. CoRR abs/2201.11220 (2022) - [i6]Sheng-Chun Kao, Hyoukjun Kwon
A Formalism of DNN Accelerator Flexibility. CoRR abs/2206.02987 (2022) - 2021
- [j7]Hyoukjun Kwon
Flexion: A Quantitative Metric for Flexibility in DNN Accelerators. IEEE Comput. Archit. Lett. 20(1): 1-4 (2021) - [c27]Hyoukjun Kwon
Heterogeneous Dataflow Accelerators for Multi-DNN Workloads. HPCA 2021: 71-83 - [i5]Ananda Samajdar, Michael Pellauer, Tushar Krishna:
Self-Adaptive Reconfigurable Arrays (SARA): Using ML to Assist Scaling GEMM Acceleration. CoRR abs/2101.04799 (2021) - 2020
- [b2]Tushar Krishna, Hyoukjun Kwon
Data Orchestration in Deep Learning Accelerators. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2020, ISBN 978-3-031-00639-5 - [j6]Hyoukjun Kwon
MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings. IEEE Micro 40(3): 20-29 (2020)
2010 – 2019
- 2019
- [c26]Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Clayton Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel S. Emer:
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration. ASPLOS 2019: 137-151 - [c25]Kartik Hegde, Hadi Asghari Moghaddam, Michael Pellauer, Neal Clayton Crago, Aamer Jaleel, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher:
ExTensor: An Accelerator for Sparse Tensor Algebra. MICRO 2019: 319-333 - [c24]Hyoukjun Kwon
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach. MICRO 2019: 754-768 - 2018
- [j5]Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi:
Full-Stack Memory Model Verification with TriCheck. IEEE Micro 38(3): 58-68 (2018) - [c23]Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons
A modular digital VLSI flow for high-productivity SoC design. DAC 2018: 72:1-72:6 - [c22]Kartik Hegde, Jiyong Yu
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition. ISCA 2018: 674-687 - [i4]Kartik Hegde, Jiyong Yu, Rohit Agrawal, Mengjia Yan, Michael Pellauer, Christopher W. Fletcher:
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition. CoRR abs/1804.06508 (2018) - [i3]Hyoukjun Kwon, Michael Pellauer, Tushar Krishna:
MAESTRO: An Open-source Infrastructure for Modeling Dataflows within Deep Learning Accelerators. CoRR abs/1805.02566 (2018) - 2017
- [c21]Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi:
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA. ASPLOS 2017: 119-133 - [c20]Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer:
RTLcheck: verifying the memory consistency of RTL designs. MICRO 2017: 463-476 - 2016
- [i2]Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi:
Exploring the Trisection of Software, Hardware, and ISA in Memory Model Design. CoRR abs/1608.07547 (2016) - [i1]Yatin A. Manerkar, Caroline Trippel, Daniel Lustig, Michael Pellauer, Margaret Martonosi:
Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings. CoRR abs/1611.01507 (2016) - 2015
- [j4]Daniel Lustig, Michael Pellauer, Margaret Martonosi:
Verifying Correct Microarchitectural Enforcement of Memory Consistency Models. IEEE Micro 35(3): 72-82 (2015) - [j3]Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer:
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. ACM Trans. Comput. Syst. 33(3): 10:1-10:32 (2015) - [c19]Daniel Lustig, Caroline Trippel, Michael Pellauer, Margaret Martonosi:
ArMOR: defending against memory consistency model mismatches in heterogeneous architectures. ISCA 2015: 388-400 - [c18]Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi:
CCICheck: using µhb graphs to verify the coherence-consistency interface. MICRO 2015: 26-37 - 2014
- [j2]Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Efficient Spatial Processing Element Control via Triggered Instructions. IEEE Micro 34(3): 120-137 (2014) - [c17]Daniel Lustig, Michael Pellauer, Margaret Martonosi:
Pipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models. MICRO 2014: 635-646 - 2013
- [c16]Michel A. Kinsy, Michael Pellauer, Srinivas Devadas:
Heracles: a tool for fast RTL-based design space exploration of multicore processors. FPGA 2013: 125-134 - [c15]Peng Li
A Hierarchical Architectural Framework for Reconfigurable Logic Computing. IPDPS Workshops 2013: 287-292 - [c14]Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Triggered instructions: a control paradigm for spatially-programmed architectures. ISCA 2013: 142-153 - 2012
- [c13]Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer:
Leveraging latency-insensitivity to ease multiple FPGA design. FPGA 2012: 175-184 - 2011
- [b1]Michael Pellauer:
Cycle-accurate multicore performance models on FPGAs. Massachusetts Institute of Technology, Cambridge, MA, USA, 2011 - [c12]Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer:
Leap scratchpads: automatic memory and cache management for reconfigurable logic. FPGA 2011: 25-28 - [c11]Michel A. Kinsy, Michael Pellauer, Srinivas Devadas:
Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System. FPL 2011: 356-362 - [c10]Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer:
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. HPCA 2011: 406-417 - 2010
- [c9]Nirav Dave, Man Cheuk Ng, Michael Pellauer, Arvind:
A design flow based on modular refinement. MEMOCODE 2010: 11-20 - [c8]Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer
Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID). MEMOCODE 2010: 69-72
2000 – 2009
- 2009
- [j1]Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer:
A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(3): 16:1-16:26 (2009) - [c7]Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer:
Soft connections: addressing the hardware-design modularity problem. DAC 2009: 276-281 - 2008
- [c6]Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer:
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. FPGA 2008: 87-96 - [c5]Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer:
Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. ISPASS 2008: 1-10 - 2007
- [c4]Nirav Dave, Arvind, Michael Pellauer:
Scheduling as Rule Composition. MEMOCODE 2007: 51-60 - [c3]Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan:
Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA. MEMOCODE 2007: 97-100 - 2006
- [c2]Nirav Dave, Michael Pellauer, S. Gerding, Arvind:
802.11a transmitter: a case study in microarchitectural exploration. MEMOCODE 2006: 59-68 - 2005
- [c1]Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyur S. Nikhil:
Synthesis of synchronous assertions with guarded atomic actions. MEMOCODE 2005: 15-24
Coauthor Index
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