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Song Jia
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2020 – today
- 2024
- [j20]Xin Qiao
, Youming Yang
An eDRAM-Based Computing-in-Memory Macro With Full-Valid-Storage and Channel-Wise-Parallelism for Depthwise Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2539-2543 (2024) - 2023
- [j19]Yuwen Liu
A label noise filtering and label missing supplement framework based on game theory. Digit. Commun. Networks 9(4): 887-895 (2023) - [j18]Bingyi Ye
A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS. IEEE J. Solid State Circuits 58(1): 19-29 (2023) - 2022
- [j17]Haibo Ge
LEO Enhanced Global Navigation Satellite System (LeGNSS): progress, opportunities, and challenges. Geo spatial Inf. Sci. 25(1): 1-13 (2022) - [c23]Xiaotong Zhao, Song Jia, Xiaoxia Yang, Chengming Zhang, Hui Wang:
Research on Intelligent Alarm Garbage Processing System Based on Internet of Things. AIoTC 2022: 40-45 - [c22]Bingyi Ye, Kai Sheng
A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS. ISSCC 2022: 118-120 - 2021
- [i1]Wenwen Gong, Huiping Wu, Xiaokang Wang, Xuyun Zhang, Yifei Chen, Song Jia, Mohammad Reza Khosravi:
Diversity-aware Web APIs Assignment and Recommendation for Mashup Creation with Compatibility Guarantee. CoRR abs/2107.10538 (2021) - 2020
- [c21]Xiaoxia Yang, Song Jia, Chengming Zhang:
A Prediction Method for Soil Moisture Time Series. ML4CS (3) 2020: 526-537
2010 – 2019
- 2019
- [j16]Xu Hui, Bailing Wang, Song Jia
An algorithm for calculating coverage rate of WSNs based on geometry decomposition approach. Peer-to-Peer Netw. Appl. 12(3): 568-576 (2019) - [c20]Xinning Liu, Song Jia, Hanzun Zhang:
A Novel High-speed FPGA-based True Random Number Generator Based on Chaotic Ring Oscillator. ASICON 2019: 1-4 - [c19]Sheng Zhang, Song Jia, Hanzun Zhang, Rongshan Wei, Weixin Gai:
Design of an Adaptive Loop Gain Controller Based on Auto-correlation Detection Scheme in All-Digital Phase-Locked Loop. ASICON 2019: 1-4 - 2018
- [j15]Yuan Wang
A 1-Gbps reference-less burst-mode CDR with embedded TDC in a 65-nm CMOS process. Int. J. Circuit Theory Appl. 46(8): 1565-1576 (2018) - 2017
- [j14]Yuan Wang
Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process. Int. J. Circuit Theory Appl. 45(6): 851-858 (2017) - [c18]Zizhao Liu, Tao Pan, Song Jia, Uan Wang:
Design of a novel ternary SRAM sense amplifier using CNFET. ASICON 2017: 207-210 - [c17]Yunfan Yang, Song Jia, Yuan Wang
A reliable true random number generator based on novel chaotic ring oscillator. ISCAS 2017: 1-4 - 2016
- [j13]Yuan Wang
Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process. Sci. China Inf. Sci. 59(4): 042407:1-042407:9 (2016) - [j12]Wenyi Tang, Song Jia, Yuan Wang
A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis. IEICE Trans. Electron. 99-C(8): 956-962 (2016) - [j11]Yuan Wang
A 4.8-6.8 GHz low phase noise LC VCO in 0.13-µm CMOS technology. Int. J. Circuit Theory Appl. 44(9): 1758-1764 (2016) - [j10]Song Jia, Ziyi Wang, Shilin Yan, Yuan Wang
A true single-phase clock dual-modulus prescaler with enhanced robustness against leakage currents. Int. J. Circuit Theory Appl. 44(10): 1895-1900 (2016) - [c16]Yuan Wang
Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics. ISCAS 2016: 1-4 - [c15]Guangyi Lu, Yuan Wang
A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications. ISCAS 2016: 265-268 - [c14]Song Jia, Ziyi Wang, Zijin Li, Yuan Wang
A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic. ISCAS 2016: 2751-2754 - 2015
- [j9]Guangyi Lu, Yuan Wang
Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling. Sci. China Inf. Sci. 58(4): 1-9 (2015) - [j8]Song Jia, Shigong Lyu, Xiayu Li, Li Liu, Yandong He:
Simplified carry save adder-based array multiplier scheme and circuits design. Int. J. Circuit Theory Appl. 43(9): 1226-1234 (2015) - [c13]Jiyu Chen, Song Jia, Yuan Wang:
A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier. ASICON 2015: 1-4 - [c12]Fangyuan Dang, Yuan Wang
Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation. ASICON 2015: 1-4 - [c11]Song Jia, Weiting Li, Wenyi Tang, Yuan Wang
A low power and high speed CAM design using pulsed voltage for search-line. ASICON 2015: 1-4 - [c10]Mengyin Jiang, Yuan Wang
A reference-less all-digital burst-mode CDR with embedded TDC. ASICON 2015: 1-4 - [c9]Song Jia, Shilin Yan, Yuan Wang
A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic. ISCAS 2015: 890-893 - [c8]Yuequan Liu, Yuan Wang
180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance. ISCAS 2015: 1394-1397 - 2013
- [j7]Song Jia, Li Liu, Xiayu Li, Fengfeng Wu, Yuan Wang
Data Convertors Design for Optimization of the DDPL Family. IEICE Trans. Electron. 96-C(9): 1195-1200 (2013) - [j6]Song Jia, Heqing Xu, Fengfeng Wu, Yuan Wang:
A Current-Mirror Winner-Take-All Sense Amplifier for Low Voltage SRAMs. IEICE Trans. Electron. 96-C(9): 1205-1207 (2013) - [j5]Fengfeng Wu, Song Jia, Qinglong Meng, Shigong Lv, Yuan Wang
Improved CRC Calculation Strategies for 64-bit Serial RapidIO. IEICE Trans. Electron. 96-C(10): 1330-1338 (2013) - [c7]Baoguang Liu, Yuan Wang
A novel dynamic element match technique in current-steering DAC. ASICON 2013: 1-4 - [c6]Guangyi Lu, Yuan Wang
Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits. ASICON 2013: 1-4 - [c5]Heqing Xu, Song Jia, Jiyu Chen, Yuan Wang
A current mode sense amplifier with self-compensation circuit for SRAM application. ASICON 2013: 1-4 - 2012
- [j4]Xiayu Li, Song Jia, Limin Liu, Yuan Wang
Design of novel, semi-transparent flip-flops (STFF) for high speed and low power application. Sci. China Inf. Sci. 55(10): 2390-2398 (2012) - [j3]Xiayu Li, Song Jia, Limin Liu, Yuan Wang
A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF). IEICE Trans. Electron. 95-C(6): 1125-1127 (2012) - 2011
- [j2]Hongyi Li, Yuan Wang
Novel single-loop multi-bit sigma-delta modulator using OTA sharing technique without DEM. IEICE Electron. Express 8(24): 2041-2047 (2011) - [c4]Peng Zhang, Yuan Wang
A novel multi-finger layout strategy for GGnMOS ESD protection device. ASICON 2011: 275-278 - 2010
- [j1]Fengfeng Wu, Song Jia, Yuan Wang
Low swing drivers based on charge redistribution. Sci. China Inf. Sci. 53(11): 2377-2388 (2010) - [c3]Xiaoxia Yang, Yong Liang, Song Jia:
The Application of Three-Dimensional Visualization Technology in Village Information Service Platform. CCTA (3) 2010: 41-45 - [c2]Xiaoxia Yang, Yong Liang, Song Jia:
Study on the Rainfall Interpolation Algorithm of Distributed Hydrological Model Based on RS. CCTA (2) 2010: 700-705
2000 – 2009
- 2003
- [c1]Ling Liu, Wennan Feng, Song Jia, Anping Jiang, Lijiu Ji:
Design Retargetable Platform System for Microprocessor Functional Test. Asian Test Symposium 2003: 458-461
Coauthor Index
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