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Guangyi Lu
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- affiliation: Peking University, Beijing, China
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2020 – today
- 2023
- [j10]Jiahao Wei, Weiqi Chen
, Yajie Gong, Qi Wu
Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4413-4422 (2023) - 2020
- [j9]Yize Wang
A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics. IEEE Access 8: 64730-64738 (2020)
2010 – 2019
- 2018
- [c6]Guangyi Lu, Yuan Wang, Lizhong Zhang, Yize Wang, Ru Huang, Xing Zhang:
Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. ISCAS 2018: 1-5 - 2017
- [j8]Yize Wang, Yuan Wang
A novel TLP-based method to deliver IEC 61000-4-2 ESD stress. IEICE Electron. Express 14(9): 20170163 (2017) - [j7]Yuan Wang
Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness. IEICE Trans. Electron. 100-C(3): 344-347 (2017) - [c5]Guangyi Lu, Yuan Wang
Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process. ISCAS 2017: 1-4 - 2016
- [j6]Yuan Wang
Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process. Sci. China Inf. Sci. 59(4): 042407:1-042407:9 (2016) - [j5]Jian Cao, Jingya Xu, Yuan Wang
A compact SCR model using advanced BJT models and standard SPICE elements. Sci. China Inf. Sci. 59(10): 109302 (2016) - [j4]Guangyi Lu, Yuan Wang
Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process. Sci. China Inf. Sci. 59(12): 122401:1-122401:9 (2016) - [j3]Jian Cao, Yize Wang, Yuan Wang
A novel SPICE circuit model of electrostatic discharge (ESD) generator. IEICE Electron. Express 13(9): 20160238 (2016) - [j2]Guangyi Lu, Yuan Wang
Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process. IEICE Trans. Electron. 99-C(5): 590-596 (2016) - [c4]Guangyi Lu, Yuan Wang
A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications. ISCAS 2016: 265-268 - 2015
- [j1]Guangyi Lu, Yuan Wang
Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling. Sci. China Inf. Sci. 58(4): 1-9 (2015) - [c3]Jian Cao, Zhenxu Ye, Yuan Wang
A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network. ASICON 2015: 1-4 - [c2]Nan Han, Yuan Wang
Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection. ASICON 2015: 1-4 - 2013
- [c1]Guangyi Lu, Yuan Wang
Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits. ASICON 2013: 1-4
Coauthor Index
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