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Hung Tien Bui
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2010 – 2019
- 2013
- [c14]Marcel Siadjine Njinowa, Hung Tien Bui, François-Raymond Boyer:
Design of low power 4-bit flash ADC based on standard cells. NEWCAS 2013: 1-4 - 2012
- [c13]Hung Tien Bui:
Pipelined FPGA design of the Goertzel algorithm for exon prediction. ISCAS 2012: 572-575 - 2011
- [c12]Michel Voyer, Sylvain-Robert Rivard, Luc Morin, Hung Tien Bui:
Rapid prototyping of the Goertzel algorithm for hardware acceleration of exon prediction. ISCAS 2011: 85-88 - 2010
- [c11]Jogendra Singh Thongam, Pierre Bouchard, Valentin Giurgiu, Hung Tien Bui, Mohand A. Ouhrouche:
Sensorless vector control of PMSG for variable speed wind energy applications. CCECE 2010: 1-5 - [c10]Marcel Siadjine Njinowa, Hung Tien Bui, François R. Boyer:
Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS). ISCAS 2010: 1312-1315
2000 – 2009
- 2008
- [j1]Hung Tien Bui, Yvon Savaria:
Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(3): 766-774 (2008) - [c9]Hung Tien Bui:
High speed CDR using a novel binary phase detector with probable-lock-detection. ICECS 2008: 1006-1009 - [c8]Hung Tien Bui:
Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis. ISCAS 2008: 3422-3425 - 2007
- [c7]Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria:
A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. ISCAS 2007: 633-636 - 2006
- [c6]Hung Tien Bui:
Dual-Path and Diode-Tracking Active Inductors for MCML Gates. CCECE 2006: 1060-1063 - [c5]Hung Tien Bui, Yvon Savaria:
High speed differential pulse-width control loop based on frequency-to-voltage converters. ACM Great Lakes Symposium on VLSI 2006: 53-56 - 2005
- [c4]Hung Tien Bui, Yvon Savaria:
A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs. IWSOC 2005: 557-562 - 2004
- [c3]Hung Tien Bui, Yvon Savaria:
Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector. ISCAS (4) 2004: 369-372 - [c2]Hung Tien Bui, Yvon Savaria:
10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS. IWSOC 2004: 115-118 - 2001
- [c1]Abdulkarim Al-Sheraidah, Bassem Alhalabi, Hung Tien Bui:
Five new high-performance multiplexer-based 1-bit full adder cells. ICECS 2001: 807-810
Coauthor Index
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