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Giuseppe Natale
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2020 – today
- 2024
- [i1]Giuseppe Natale:
On the Computation of 2-Dimensional Recurrence Equations. CoRR abs/2406.02082 (2024) - 2021
- [j3]Enrico Reggiani, Emanuele Del Sozzo
, Davide Conficconi
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components. ACM Trans. Reconfigurable Technol. Syst. 14(3): 15:1-15:33 (2021) - 2020
- [j2]Luca Stornaiuolo, Filippo Carloni
Enabling transparent hardware acceleration on Zynq SoC for scientific computing. SIGBED Rev. 17(1): 30-35 (2020)
2010 – 2019
- 2019
- [b1]Giuseppe Natale:
On how to design optimized spatial architectures: from iterative stencils to convolutional neural networks. Polytechnic University of Milan, Italy, 2019 - 2018
- [c9]Enrico Reggiani, Giuseppe Natale, Carlo Moroni, Marco D. Santambrogio:
An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils. IPDPS Workshops 2018: 115-122 - [c8]Niccolo Raspa, Giuseppe Natale, Marco Bacis, Marco D. Santambrogio:
A Framework with Cloud Integration for CNN Acceleration on FPGA Devices. IPDPS Workshops 2018: 170-177 - 2017
- [c7]Marco Rabozzi, Giuseppe Natale, Emanuele Del Sozzo
Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project. DATE 2017: 410-415 - [c6]Alessandro Pappalardo, Giuseppe Natale, Marco Domenico Santambrogio:
A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains. DSD 2017: 151-154 - [c5]Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele
Optimizing streaming stencil time-step designs via FPGA floorplanning. FPL 2017: 1-4 - [c4]Marco Bacis, Giuseppe Natale, Emanuele Del Sozzo
A Pipelined and Scalable Dataflow Implementation of Convolutional Neural Networks on FPGA. IPDPS Workshops 2017: 90-97 - [c3]Marco Rabozzi, Rolando Brondolin, Giuseppe Natale, Emanuele Del Sozzo
A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project. ISVLSI 2017: 368-373 - [c2]Giuseppe Natale, Marco Bacis, Marco Domenico Santambrogio:
On How to Design Dataflow FPGA-Based Accelerators for Convolutional Neural Networks. ISVLSI 2017: 639-644 - 2016
- [j1]Riccardo Cattaneo
On How to Accelerate Iterative Stencil Loops: A Scalable Streaming-Based Approach. ACM Trans. Archit. Code Optim. 12(4): 53:1-53:26 (2016) - [c1]Giuseppe Natale, Giulio Stramondo, Pietro Bressana, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio:
A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops. ICCAD 2016: 77
Coauthor Index
aka: Marco Domenico Santambrogio
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