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Behzad Dehlaghi
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2010 – 2019
- 2019
- [c3]Shayan Shahramian
, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS. ISSCC 2019: 482-484 - 2016
- [j3]Behzad Dehlaghi
A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication. IEEE J. Solid State Circuits 51(11): 2690-2701 (2016) - [j2]Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone
Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5~µs. IEEE J. Solid State Circuits 51(12): 3192-3203 (2016) - [c2]Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone
23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs. ISSCC 2016: 410-411 - 2015
- [c1]Behzad Dehlaghi, Anthony Chan Carusone
A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS. CICC 2015: 1-4 - 2014
- [j1]Behzad Dehlaghi, Sebastian Magierowski, Leonid Belostotski
A 12.5-Gb/s On-Chip Oscilloscope to Measure Eye Diagrams and Jitter Histograms of High-Speed Signals. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1127-1137 (2014)
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