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Masami Nakajima
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2010 – 2019
- 2016
- [c9]Masami Nakajima, Ichiro Naka, Fumihiro Matsushima, Tadaaki Yamauchi:
A 20uA/MHz at 200MHz microcontroller with low power memory access scheme for small sensing nodes. COOL Chips 2016: 1-3 - 2011
- [j8]Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto:
A Scalable Massively Parallel Processor for Real-Time Image Processing. IEEE J. Solid State Circuits 46(10): 2363-2373 (2011) - [c8]Yushi Moko, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa
, Masami Nakajima, Kazutami Arimoto:
Implementation and evaluation of FAST corner detection on the massively parallel embedded processor MX-G. CVPR Workshops 2011: 157-162 - 2010
- [c7]Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto:
A scalable massively parallel processor for real-time image processing. ISSCC 2010: 334-335
2000 – 2009
- 2009
- [j7]Hiroyuki Kondo, Sugako Otani, Masami Nakajima, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Satoshi Imasu, Nobuhiro Kinoshita, Yusuke Ota, Kazutami Arimoto, Toru Shimizu:
Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications. IEEE J. Solid State Circuits 44(8): 2251-2259 (2009) - 2008
- [j6]Hiroyuki Kondo, Masami Nakajima, Norio Masui, Sugako Otani, Naoto Okumura, Yukari Takata, Takashi Nasu, Hirokazu Takata, Takashi Higuchi, Mamoru Sakugawa, Hayato Fujiwara, Kazuya Ishida, Koichi Ishimi, Satoshi Kaneko, Teruyuki Itoh, Masayuki Sato, Osamu Yamamoto, Kazutami Arimoto:
Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors. IEEE J. Solid State Circuits 43(4): 892-901 (2008) - [c6]Hiroyuki Kondo, Masami Nakajima, Sugako Otani, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Kazuhiro Inaoka, Yoshihiro Saito, Kazutami Arimoto, Toru Shimizu:
Heterogeneous multicore SoC for secure multimedia applications. CICC 2008: 675-678 - 2007
- [j5]Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu:
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. IEEE J. Solid State Circuits 42(1): 183-192 (2007) - [j4]Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto:
The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. IEEE J. Solid State Circuits 42(4): 804-812 (2007) - [c5]Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto:
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL 2007: 43 - 2006
- [j3]Toru Shimizu, Masami Nakajima, Masahiro Kainaga:
Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture. IEICE Trans. Electron. 89-C(11): 1512-1518 (2006) - [c4]Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu:
A 40GOPS 250mW massively parallel processor based on matrix architecture. ISSCC 2006: 1616-1625 - 2005
- [j2]Hiroyuki Kondo, Masami Nakajima, Miroslaw Bober, Krzysztof Kucharski, Osamu Yamamoto, Toru Shimizu:
Implementation of Face Recognition Processing Using an Embedded Processor. J. Robotics Mechatronics 17(4): 428-436 (2005) - 2004
- [j1]Satoshi Kaneko, Hiroyuki Kondo, Norio Masui, Koichi Ishimi, Teruyuki Itou, Masayuki Satou, Naoto Okumura, Yukari Takata, Hirokazu Takata, Mamoru Sakugawa, Takashi Higuchi, Sugako Ohtani, Kei Sakamoto, Naoshi Ishikawa, Masami Nakajima, Shunichi Iwata, Kiyoshi Hayase, Satoshi Nakano, Sachiko Nakazawa, Kunihiro Yamada, Toru Shimizu:
A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory. IEEE J. Solid State Circuits 39(1): 184-193 (2004)
1990 – 1999
- 1996
- [c3]Masami Nakajima, Michitaka Kameyama:
Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy. ISMVL 1996: 104-109 - 1994
- [c2]Masami Nakajima, Michitaka Kameyama:
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations. ISMVL 1994: 223-230 - 1993
- [c1]Masami Nakajima, Michitaka Kameyama:
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations. ISMVL 1993: 283-288
Coauthor Index
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