default search action
International Journal of Reconfigurable Computing, Volume 2014
Volume 2014, 2014
- Guillermo A. Jaquenod, Javier Valls
, Javier Siman:
Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain. 546264:1-546264:5 - Sharad Sinha
IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance. 418750:1-418750:17 - Alp Kiliç
A Top-Down Optimization Methodology for Mutually Exclusive Applications. 827613:1-827613:18 - Beau J. Tippetts, Dah-Jye Lee, Kirt D. Lillywhite, James K. Archibald:
Hardware-Efficient Design of Real-Time Profile Shape Matching Stereo Vision Algorithm on FPGA. 945926:1-945926:12 - Naveed Imran, Ronald F. DeMara
Distance-Ranked Fault Identification of Reconfigurable Hardware Bitstreams via Functional Input. 279673:1-279673:21 - Tim Todman
Using Statistical Assertions to Guide Self-Adaptive Systems. 724585:1-724585:8 - Senoj Joseph Olakkenghil, K. Baskaran:
An FPGA Task Placement Algorithm Using Reflected Binary Gray Space Filling Curve. 495080:1-495080:7 - Leonid V. Moroz
Simple Hybrid Scaling-Free CORDIC Solution for FPGAs. 615472:1-615472:4 - Vanderlei Bonato
Practical Education Fostered by Research Projects in an Embedded Systems Course. 287205:1-287205:12 - Mouna Ben Said, Yessine Hadj Kacem
Design Patterns for Self-Adaptive RTE Systems Specification. 536362:1-536362:21 - Ariane Keller, Daniel Borkmann, Stephan Neuhaus, Markus Happe
Self-Awareness in Computer Networks. 692076:1-692076:16 - Kaiyu Wang, Zhiming Song
FPGA-Based Implementation of All-Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator. 502942:1-502942:15 - Sharad Sinha
Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis. 564924:1-564924:14 - Spencer G. Fowers, Alok Desai
TreeBASIS Feature Descriptor and Its Hardware Implementation. 606210:1-606210:12 - Mohsin Amin
Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System. 806237:1-806237:8 - Mouna Baklouti
Multi-Softcore Architecture on FPGA. 979327:1-979327:13 - Gayathri R. Prabhu, Bibin Johnson, J. Sheeba Rani:
Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration. 243835:1-243835:9
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-17 20:48 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: