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"Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain."

Guillermo A. Jaquenod, Javier Valls, Javier Siman (2014)

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DOI: 10.1155/2014/546264

access: open

type: Journal Article

metadata version: 2020-04-02

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  dblp key:
  - journals/ijrc/JaquenodVS14
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  - https://dblp.org/rec/journals/ijrc/JaquenodVS14
Guillermo A. Jaquenod, Javier Valls, Javier Siman:
Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain. Int. J. Reconfigurable Comput. 2014: 546264:1-546264:5 (2014)

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