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33rd SBCCI 2020: Campinas, Brazil
- 33rd Symposium on Integrated Circuits and Systems Design, SBCCI 2020, Campinas, Brazil, August 24-28, 2020. IEEE 2020, ISBN 978-1-7281-9625-1
- Evandro C. Ferraz, José V. O. Júnior, Ian Andrew Grout, Alexandre C. R. da Silva:
Synthesis and Optimization of Majority Expressions through a Mathematical Model. 1-6 - Garrenlus de Souza, Sergio Bampi
, Arthur Cerveira, Bruno Zatt, Felipe Sampaio:
Evaluation of Cache-Based Memory Hierarchy for HEVC Video Decoding. 1-6 - Vanessa F. de Lima, Rodrigo Ataide, Sergio Bampi
Performance and Variability Trade-offs of CMOS PTAT Generator Topologies for Voltage Reference Applications. 1-6 - Bruno Canal, Hamilton Duarte Klimach, Sergio Bampi
Low-Voltage Dynamic Comparator with Bulk-Driven Floating Inverter Amplifier. 1-6 - Felipe G. A. e Silva, Adahil Muniz, Jarbas Silveira
CLC-A: An Adaptive Implementation of the Column Line Code (CLC) ECC. 1-6 - Luiz Neto, Marcel Moscarelli Corrêa, Daniel Palomino
Directional Intra Frame Prediction Architecture with Edge Filter and Upsampling for AV1 Video Coding. 1-6 - Talita Alves Borges, Leonardo Bandeira Soares, Cristina Meinhardt
A Fine-grained Methodology for Accuracy-configurable and Energy-efficient Gaussian Filters Design. 1-6 - João Navarro
Performance Comparison of High-Speed Dual Modulus Prescalers Using Metaheuristic Sizing/Optimization. 1-6 - Poliana A. C. Oliveira, Maria C. O. Fonte Boa, Renan A. Marks
Analysis of single-module and cascade molecular analog circuits for approximate computing based on DNA Strand Displacement. 1-6 - Duarte Lopes de Oliveira, Gabriel C. Duarte, Nicolly N. M. Cardoso, Gracieth Cavalcanti Batista:
Implementation of Asynchronous Pipelines with QDI Template onto FPGAs Using Commercial Tools. 1-5 - Julio Saraçol Domingues Júnior, Leomar Soares da Rosa Jr., Felipe de Souza Marques:
A Straightforward Methodology for QCA Circuits Design. 1-6 - Jader A. De Lima:
A 0.55-V 0.1°C-Accuracy All-CMOS Temperature Sensor for Implanted Devices. 1-6 - William Souza da Cruz
Evidence of a Dynamic Fault Model in the DICE Radiation-Hardened Cell. 1-6 - Fabian Souza de Andrade, Ana Isabela Araújo Cunha, Edson Pinto Santana, Ygor Oliveira da Guarda Souza:
A CMOS Analog Two-Layer Full Signal Range Cellular Neural Network for Image Filtering. 1-6 - Nágila Ribeiro de Menezes, Hugo Daniel Hernández
All-digital FPGA-based RF pulsed transmitter with hardware complexity reduction techniques. 1-5 - Vassilis Alimisis, Georgios Pappas, Paul P. Sotiriadis
Fractional-Order Instrumentation Amplifier Transfer Function for Control Applications. 1-6 - Guilherme T. Leal, Sandro A. P. Haddad:
The use of the analog wavelet filter to generate a sinusoidal signal and decompose the TEB signal into its cardiac and respiratory components in implantable cardiac pacemaker systems. 1-6 - Fávero Guilherme Santos
A Novel Single Propagation Path Multimode PA. 1-6 - Iaçanã I. Weber, Leonardo Londero de Oliveira, Everton Carara, Fernando Gehm Moraes
Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication. 1-6 - Gustavo Paz Platcheck
Characterization of Enclosed Layout Transistors for Analog Applications on a130nm Technology. 1-6 - Raul Silveira Silva, Guilherme Korol, Michael Guilherme Jordan, Marcelo Brandalero, Michael Hübner, Monica Magalhães Pereira, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
A Management Technique for Concurrent Access to a Reconfigurable Accelerator. 1-6 - Tiago M. de F. Lopes, Victor R. R. de Oliveira, Fernanda D. V. R. Oliveira, José Gabriel Rodríguez Carneiro Gomes:
Event-Based CMOS Image Sensor with Shared DVS Module for Pixel Area Reduction. 1-6 - Joao N. C. Fiche, Marco T. D. Sousa, Jeferson F. Chaves, Marco A. Ribeiro
Energy reduction opportunities in Field-Coupled Nanocomputing Adders. 1-6 - Hiago Rocha
Firefly: An Open-source Rocket-based Intermittent Framework. 1-6 - Rafael Follmann Faccenda
Maximizing Throughput-per-Joule of a Hybrid Communication Infrastructure Through a Software-Hardware based DVFS Mechanism. 1-6 - Alisson Linhares, Henrique Rusa, Daniel Formiga, Rodolfo Azevedo:
A SystemC profiling framework to improve fixed-point hardware utilization. 1-6 - Alzemiro Lucas da Silva, André Luís Del Mestre Martins, Fernando Gehm Moraes
Mapping and Migration Strategies for Thermal Management in Many-Core Systems. 1-6 - Francisco Carlos Silva, João P. dos S. Patrocinio, Ivan Saraiva Silva, Ricardo Pezzuol Jacobi
Design Space Exploration of a Reconfigurable Accelerator in a Heterogeneous Multicore. 1-6 - Jose L. Ramirez, Ricardo T. Yoshioka, Carolina C. P. Nunes
Model and simulation of Warpage in packaged IC strips after Mold Array Process. 1-5 - Luiz A. da Silva, Lucas Compassi Severo
A Novel Fully Integrated ULV SC DC-DC Converter for Indoor Light Energy Harvesting. 1-6 - Vanio Rodrigues Filho, Marcio Monteiro, Ismael Seidel, Mateus Grellert
Standalone Rate-Distortion FME Architecture. 1-6 - Marcelo Ruaro
Multiple-objective Management based on a Distributed SDN Architecture for Many-cores. 1-6 - Victor Oliveira Costa, Carlos Gabriel de Araujo Gewehr
Hardware Accelerator for Shapelet Distance Computation in Time-Series Classification. 1-6 - Tiago Knorst, Julio Costella Vicenzi
Unlocking the Full Potential of Heterogeneous Accelerators by Using a Hybrid Multi-Target Binary Translator. 1-6 - Alba Sandyra Bezerra Lopes, Monica Magalhães Pereira:
A Machine Learning Approach to Accelerating DSE of Reconfigurable Accelerator Systems. 1-6 - Vinicius Ruela Pereira Borges, Murilo R. Perleberg
A Hardware Design for 3D-HEVC Depth Intra Skip with Synthesized View Distortion Change. 1-6 - Roger Endrigo Carvalho Porto, Bruno Zatt, Nuno Roma
2PSA: An Optimized and Flexible Power-Precision Scalable Adder. 1-6 - Alessandro Girardi, Helmut Graeb:
Modeling and Optimization of a Microprobe Detector for Area and Yield Improvement. 1-6 - Arthur Passos, Felipe Viel
A Hardware Accelerator for the Segmentation of Hyperspectral Images. 1-5 - Vanessa F. de Lima, Hamilton Klimach:
A 37 nW MOSFET-Only Voltage Reference in 0.13 μm CMOS. 1-6
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