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Rodolfo Azevedo
Rodolfo Jardim de Azevedo
Person information
- affiliation: University of Campinas, São Paulo, Brazil
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2020 – today
- 2024
- [j31]Mauricio G. Palma
, Jorge González
Inter-Node Message Passing Through Optical Reconfigurable Memory Channel. IEEE Access 12: 83057-83071 (2024) - [j30]Lucas Castro
Exploring Dynamic Duty Cycling for Energy Efficiency in Coherent DSP ASIC. IEEE Embed. Syst. Lett. 16(2): 202-205 (2024) - [c58]Rafael Corsi Ferrão
Learn by Example in a Modern Embedded System Course. ITiCSE (2) 2024 - [c57]Rafael Corsi Ferrão
Embedded-check a Code Quality Tool for Automatic Firmware Verification. ITiCSE (1) 2024 - 2023
- [j29]Kleber Kruger
DONUTS: An efficient method for checkpointing in non-volatile memories. Concurr. Comput. Pract. Exp. 35(18) (2023) - [j28]Ricardo Caceffo
Perceptual Learning Modules (PLM) in CS1: a Negative Result and a Methodological Warning. J. Univers. Comput. Sci. 29(9): 988-1009 (2023) - [j27]Lucas Exposto Soares
Usabilidade dos Ambientes Virtuais de Aprendizagem Canvas e Blackboard: Caso de estudo em uma Universidade Brasileira. Revista Brasileira de Informática na Educ. 31: 149-173 (2023) - [j26]Eryck Pedro da Silva
A Syllabi Analysis of CS1 Courses from Brazilian Public Universities. Revista Brasileira de Informática na Educ. 31: 407-436 (2023) - [j25]Eryck Pedro da Silva
When Test Cases Are Not Enough: Identification, Assessment, and Rationale of Misconceptions in Correct Code (MC³). Revista Brasileira de Informática na Educ. 31: 1165-1199 (2023) - [c56]Kleber Kruger, Ricardo Pannain, Rodolfo Azevedo:
Using Logging-on-Write to Improve Non-Volatile Memory Checkpoints via Processing-in-Memory. SBAC-PAD 2023: 68-77 - 2022
- [j24]Jorge González
Optically connected memory for disaggregated data centers. J. Parallel Distributed Comput. 163: 300-312 (2022) - [c55]Eduardo C. Oliveira, Ronaldo C. M. Correia, Rodolfo Azevedo, Simone Telles, Alessandra A. Macedo
A Computational Thinking Course for Pre-Service Teachers. EDUCON 2022: 1082-1088 - [c54]Rafael Corsi Ferrão, Igor dos Santos Montagner
How much C can students learn in one week? Experiences teaching C in advanced CS courses. FIE 2022: 1-8 - [c53]Jonathas Silveira, Lucas Castro, Victor Araújo, Rodrigo Zeli, Daniel Lazari, Marcelo Guedes, Rodolfo Azevedo, Lucas Wanner:
Prof5: A RISC-V profiler tool. SBAC-PAD 2022: 201-210 - 2020
- [j23]Isaías B. Felzmann
ADeLe: A description language for approximate hardware. Future Gener. Comput. Syst. 102: 245-258 (2020) - [j22]João Fabrício Filho
AxRAM: A lightweight implicit interface for approximate data access. Future Gener. Comput. Syst. 113: 556-570 (2020) - [j21]Ewerton Silva, Ricardo da Silva Torres
Application-Oriented Retinal Image Models for Computer Vision. Sensors 20(13): 3746 (2020) - [c52]Jorge González, Alexander Gazman, Maarten Hattink, Mauricio G. Palma
Optically Connected Memory for Disaggregated Data Centers. SBAC-PAD 2020: 43-50 - [c51]Alisson Linhares, Henrique Rusa, Daniel Formiga, Rodolfo Azevedo:
A SystemC profiling framework to improve fixed-point hardware utilization. SBCCI 2020: 1-6 - [c50]Bruno Bonotto
Bringing Energy Information to the Instruction Set. SBESC 2020: 1-8 - [i2]Jorge González, Alexander Gazman, Maarten Hattink, Mauricio G. Palma, Meisam Bahadori, Ruth Rubio-Noriega, Lois Orosa, Madeleine Glick, Onur Mutlu, Keren Bergman, Rodolfo Azevedo:
Optically Connected Memory for Disaggregated Data Centers. CoRR abs/2008.10802 (2020)
2010 – 2019
- 2019
- [j20]Leandro Poloni Dantas
A Novel Processor Architecture With a Hardware Microkernel to Improve the Performance of Task-Based Systems. IEEE Embed. Syst. Lett. 11(2): 46-49 (2019) - [j19]Lois Orosa
AVPP: Address-first Value-next Predictor with Value Prefetching for Improving the Efficiency of Load Value Prediction. ACM Trans. Archit. Code Optim. 15(4): 49:1-49:30 (2019) - [c49]Ricardo Caceffo, Pablo Frank-Bolton, Renan Souza, Rodolfo Azevedo:
Identifying and Validating Java Misconceptions Toward a CS1 Concept Inventory. ITiCSE 2019: 23-29 - [c48]Alisson Carvalho, Rodolfo Azevedo:
Towards a Transprecision Polymorphic Floating-Point Unit for Mixed-Precision Computing. SBAC-PAD 2019: 56-63 - [c47]João Fabrício Filho
A Resilient Interface for Approximate Data Access. SBESC 2019: 1-8 - [i1]Lois Orosa, Yaohua Wang, Ivan Puddu, Mohammad Sadrosadati, Kaveh Razavi, Juan Gómez-Luna, Hasan Hassan, Nika Mansouri-Ghiasi, Arash Tavakkol, Minesh Patel, Jeremie S. Kim, Vivek Seshadri, Uksong Kang, Saugata Ghose, Rodolfo Azevedo, Onur Mutlu:
Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices. CoRR abs/1902.07344 (2019) - 2018
- [j18]Ricardo Santos
Dark-Silicon Aware Design Space Exploration. J. Parallel Distributed Comput. 120: 295-306 (2018) - [c46]Erik F. Anderson, Jorge González
Optically connected and reconfigurable GPU architecture for optimized peer-to-peer access. MEMSYS 2018: 257-258 - [c45]Isaías B. Felzmann
ADeLe: Rapid Architectural Simulation for Approximate Hardware. SBAC-PAD 2018: 9-16 - [c44]Ricardo Caceffo, Guilherme Gama, Rodolfo Azevedo
Exploring Active Learning Approaches to Computer Science Classes. SIGCSE 2018: 922-927 - [c43]Isaías B. Felzmann
Impact of Memory Approximation on Energy Efficiency. WSCAD 2018: 53-60 - [c42]Rafael Soares, Luis Antonioli, Emilio Francesquini
Phase Detection and Analysis among Multiple Program Inputs. WSCAD 2018: 155-161 - [c41]Vanderson Martins do Rosário, Mario Mikio Hato, Rodolfo Azevedo, Edson Borin:
A Methodology for Optimization of Interpreters. WSCAD 2018: 205-212 - 2017
- [j17]Lara S. G. Piccolo
A socially inspired energy feedback technology: challenges in a developing scenario. AI Soc. 32(3): 383-399 (2017) - [j16]Liana Dessandre Duenha, Guilherme A. Madalozzo, Fernando Gehm Moraes
Exploiting performance, dynamic power and energy scaling in full-system simulators. Concurr. Comput. Pract. Exp. 29(22) (2017) - [j15]Maxiwell Garcia
HybridVerifier: A Cross-Platform Verification Framework for Instruction Set Simulators. IEEE Embed. Syst. Lett. 9(2): 25-28 (2017) - 2016
- [j14]Liana Dessandre Duenha
MPSoCBench: A benchmark for high-level evaluation of multiprocessor system-on-chip tools and methodologies. J. Parallel Distributed Comput. 95: 138-157 (2016) - [j13]Bruno Cardoso Lopes, Leonardo Luiz Ecco, E. C. Xavier, Rodolfo Jardim de Azevedo
Design and evaluation of compact ISA extensions. Microprocess. Microsystems 40: 1-15 (2016) - [c40]Lois Orosa
Temporal frequent value locality. ASAP 2016: 147-152 - [c39]Guilherme A. Madalozzo, Liana Dessandre Duenha, Rodolfo Azevedo
Scalability evaluation in many-core systems due to the memory organization. ICECS 2016: 396-399 - [c38]Jorge González
Architecting a computer with a full optical RAM. ICECS 2016: 716-719 - [c37]Tony Santos, Ana Silva, Liana Dessandre Duenha, Ricardo Santos, Edward D. Moreno, Rodolfo Azevedo
On the Dark Silicon Automatic Evaluation on Multicore Processors. SBAC-PAD 2016: 166-173 - [c36]Ricardo Caceffo, Steven A. Wolfman, Kellogg S. Booth, Rodolfo Azevedo
Developing a Computer Science Concept Inventory for Introductory Programming. SIGCSE 2016: 364-369 - 2015
- [c35]Rodrigo Devigo, Liana Dessandre Duenha, Rodolfo Azevedo
MultiExplorer: A tool set for multicore system-on-chip design exploration. ASAP 2015: 160-161 - [c34]Bruno Cardoso Lopes, Rafael Auler, Luiz Ramos, Edson Borin, Rodolfo Azevedo
SHRINK: reducing the ISA complexity via instruction recycling. ISCA 2015: 311-322 - 2014
- [c33]Caio Hoffman, Luiz Ramos, Rodolfo Azevedo, Guido Araujo:
Wear-out analysis of Error Correction Techniques in Phase-Change Memory. DATE 2014: 1-4 - [c32]Liana Dessandre Duenha, Marcelo Guedes, Henrique Almeida, Matheus Boy, Rodolfo Azevedo
MPSoCBench: A toolset for MPSoC system level evaluation. ICSAMOS 2014: 164-171 - [c31]Rodolfo Wottrich, Rodolfo Azevedo
Cloud-based OpenMP Parallelization Using a MapReduce Runtime. SBAC-PAD 2014: 334-341 - [e1]Edward David Moreno Ordonez, Rodolfo Jardim de Azevedo, Peter R. Kinget:
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, Aracaju, Brazil, September 1-5, 2014. ACM 2014, ISBN 978-1-4503-3156-2 [contents] - 2013
- [j12]Marcelo Guedes, Rafael Auler, Liana Dessandre Duenha, Edson Borin, Rodolfo Azevedo
An automatic energy consumption characterization of processors using ArchC. J. Syst. Archit. 59(8): 603-614 (2013) - [c30]Rodolfo Azevedo
Zombie memory: extending memory lifetime by reviving dead blocks. ISCA 2013: 452-463 - 2012
- [j11]Alexandro Baldassin
A transactional runtime system for the Cell/BE architecture. J. Parallel Distributed Comput. 72(12): 1535-1546 (2012) - [j10]Reinaldo A. Bergamaschi, Leonardo Piga, Sandro Rigo, Rodolfo Azevedo
Data center power and performance optimization through global selection of P-states and utilization rates. Sustain. Comput. Informatics Syst. 2(4): 198-208 (2012) - [c29]Marcelo Guedes, Rafael Auler, Edson Borin, Rodolfo Azevedo
An ArchC approach for automatic energy consumption characterization of processors. RSP 2012: 57-63 - [c28]Alexandro Baldassin
Energy-Performance Tradeoffs in Software Transactional Memory. SBAC-PAD 2012: 147-154 - [c27]Maxiwell Garcia, Rodolfo Azevedo
Optimizing Simulation in Multiprocessor Platforms Using Dynamic-Compiled Simulation. WSCAD-SSC 2012: 80-87 - 2011
- [j9]Ricardo Edgard Caceffo, Heloisa Vieira da Rocha, Rodolfo Jardim de Azevedo:
Ferramenta de apoio para o aprendizado ativo usando dispositivos com caneta eletrônica. Revista Brasileira de Informática na Educ. 19(2) (2011) - [c26]Leonardo Piga, Reinaldo A. Bergamaschi, Felipe Klein, Rodolfo Azevedo
Empirical Web server power modeling and characterization. IISWC 2011: 75 - [c25]João Moreira, Felipe Klein, Alexandro Baldassin
Using multiple abstraction levels to speedup an MPSoC virtual platform simulator. International Symposium on Rapid System Prototyping 2011: 99-105 - 2010
- [c24]Felipe Klein, Alexandro Baldassin
STM versus lock-based systems: an energy consumption perspective. ISLPED 2010: 431-436
2000 – 2009
- 2009
- [j8]Alexandro Baldassin
Characterizing the Energy Consumption of Software Transactional Memory. IEEE Comput. Archit. Lett. 8(2): 56-59 (2009) - [j7]Ricardo Santos, Rafael Batistella, Rodolfo Azevedo
A pattern based instruction encoding technique for high performance architectures. Int. J. High Perform. Syst. Archit. 2(2): 71-80 (2009) - [j6]Felipe Klein, Roberto Leao, Guido Araujo, Luiz C. V. dos Santos
A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 660-673 (2009) - [c23]Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo Candido Xavier
SPARC16: A New Compression Approach for the SPARC Architecture. SBAC-PAD 2009: 169-176 - [c22]Felipe Klein, Alexandro Baldassin
On the energy-efficiency of software transactional memory. SBCCI 2009 - 2008
- [j5]Ricardo Santos, Rodolfo Azevedo, Guido Araujo:
Instruction Scheduling Based on Subgraph Isomorphism for a High Performance Computer Processor. J. Univers. Comput. Sci. 14(21): 3465-3480 (2008) - [c21]Felipe Goldstein, Alexandro Baldassin
A Software Transactional Memory System for an Asymmetric Processor Architecture. SBAC-PAD 2008: 175-182 - 2007
- [c20]Felipe Klein, Guido Araujo, Rodolfo Azevedo
A multi-model power estimation engine for accuracy optimization. ISLPED 2007: 280-285 - [c19]Richard Maciel, Bruno C. Albertini
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation. ISVLSI 2007: 351-356 - [c18]Felipe Klein, Guido Araujo, Rodolfo Azevedo
On the Limitations of Power Macromodeling Techniques. ISVLSI 2007: 395-400 - [c17]Fernando Kronbauer, Alexandro Baldassin
A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation. IEEE International Workshop on Rapid System Prototyping 2007: 123-129 - 2006
- [c16]Ricardo Santos, Rodolfo Azevedo
2D-VLIW: An Architecture Based on the Geometry of Computation. ASAP 2006: 87-94 - [c15]Ricardo Santos, Rodolfo Azevedo
Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach. IPDPS 2006 - 2005
- [j4]Guido Araujo, Edna Barros
A SystemC-only design methodology and the CINE-IP multimedia platform. Des. Autom. Embed. Syst. 10(2-3): 181-202 (2005) - [j3]Cristiano C. de Araújo, Millena Gomes, Edna Barros
Platform designer: An approach for modeling multiprocessor platforms based on SystemC. Des. Autom. Embed. Syst. 10(4): 253-283 (2005) - [j2]Rodolfo Azevedo
The ArchC Architecture Description Language and Tools. Int. J. Parallel Program. 33(5): 453-484 (2005) - [c14]Cristiano C. de Araújo, Edna Barros, Rodolfo Azevedo, Guido Araujo:
Processor Centric Specification and Modelling of MPSoCs. FDL 2005: 303-315 - [c13]Eduardo Braulio Wanderley Netto, Eduardo Afonso Billo, Rodolfo Azevedo:
Exploiting the Area X Performance Trade-off with Code Compression. SoC 2005: 42-45 - [c12]Felipe Klein, Rodolfo Azevedo, Guido Araujo:
High-Level Switching Activity Prediction Through Sampled Monitored Simulation. SoC 2005: 161-166 - [c11]Eduardo Afonso Billo, Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, Eduardo Braulio Wanderley Netto:
Design of a decompressor engine on a SPARC processor. SBCCI 2005: 110-114 - 2004
- [c10]Eduardo Braulio Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo:
Multi-profile based code compression. DAC 2004: 244-249 - [c9]Pablo Viana, Edna Barros
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology. DATE 2004: 734-735 - [c8]Edson Borin, Felipe Klein, Nahri Moreano, Rodolfo Azevedo, Guido Araujo:
Fast instruction set custornization. ESTIMedia 2004: 53-58 - [c7]Eduardo Braulio Wanderley Netto, Rodolfo Azevedo
Multi-Profile Instruction Based Compression. SBAC-PAD 2004: 23-29 - [c6]Sandro Rigo, Guido Araujo, Marcus Bartholomeu, Rodolfo Azevedo
ArchC: A SystemC-Based Architecture Description Language. SBAC-PAD 2004: 66-73 - [c5]Marcus Bartholomeu, Rodolfo Azevedo
Optimizations for Compiled Simulation Using Instruction Type Information. SBAC-PAD 2004: 74-81 - [c4]Sandro Rigo, Marcio Juliato, Rodolfo Azevedo
Teaching computer architecture using an architecture description language. WCAE 2004: 6 - 2003
- [c3]Eduardo Braulio Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo:
Mixed static/dynamic profiling for dictionary based code compression. SoC 2003: 159-163 - [c2]Pablo Viana, Edna Barros
Exploring Memory Hierarchy with ArchC. SBAC-PAD 2003: 2-9 - 2002
- [b1]Rodolfo Jardim de Azevedo:
Uma arquitetura para execução de codigo comprimido em sistemas dedicados. University of Campinas, Brazil, 2002 - 2001
- [c1]Marcio Buss, Rodolfo Azevedo
Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures. CASES 2001: 141-148 - 2000
- [j1]Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo
Expression-tree-based algorithms for code compression on embedded RISC architectures. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 530-533 (2000)
Coauthor Index
Guido Araujo
aka: Guido Araújo
aka: Guido Araújo
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last updated on 2024-07-20 20:29 CEST by the dblp team
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