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12th PATMOS 2002: Seville, Spain
- Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido:
Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002. Lecture Notes in Computer Science 2451, Springer 2002, ISBN 3-540-44143-3
Opening
- Christian Piguet:
The First Quartz Electronic Watch. 1-15
Arithmetics
- Domenik Helms, Eike Schmidt, Arne Schulz, Ansgar Stammermann, Wolfgang Nebel:
An Improved Power Macro-Model for Arithmetic Datapath Components. 16-24 - Hoang Q. Dao, Vojin G. Oklobdzija:
Performance Comparison of VLSI Adders Using Logical Effort. 25-34 - Francesco Pessolano, Joep L. W. Kessels, Ad M. G. Peeters:
MDSP: A High-Performance Low-Power DSP Architecture. 35-44
Low-Level Modeling and Characterization
- Juan Antonio Carballo, Sani R. Nassif:
Impact of Technology in Power-Grid-Induced Noise. 45-54 - Armin Windschiegl, Paul Zuber, Walter Stechele:
Exploiting Metal Layer Characteristics for Low-Power Routing. 55-64 - Fabrice Picot, Philippe Coll, Daniel Auvergne:
Crosstalk Measurement Technique for CMOS ICs. 65-70 - Spiridon Nikolaidis, Nikolaos Kavvadias, Periklis Neofotistos, K. Kosmatopoulos, Theodore Laopoulos, Labros Bisdounis:
Instrumentation Set-up for Instruction Level Power Modeling. 71-80
Asynchronous and Adiabatic Techniques
- Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard:
Low-Power Asynchronous A/D Conversion. 81-91 - Igor Lemberski, Mark B. Josephs
:
Optimal Two-Level Delay - Insensitive Implementation of Logic Functions. 92-100 - Christoph Saas, Josef A. Nossek:
Resonant Multistage Charging of Dominant Capacitances. 101-107 - Oscar Garnica
A New Methodology to Design Low-Power Asynchronous Circuits. 108-117 - Antonio Blotti, Maurizio Castellucci, Roberto Saletti:
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library. 118-127
CAD Tools and Algorithms
- Vojin G. Oklobdzija:
Clocking and Clocked Storage Elements in Multi-GHz Environment. 128-145 - Torsten Mahnke, Walter Stechele, Wolfgang Hoeld:
Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment. 146-155 - Alexis Landrault, Ludovic Pellier, Alexandre Richard, Christian Jay, Michel Robert, Daniel Auvergne:
Transistor Level Synthesis Dedicated to Fast I.P. Prototyping. 156-166 - Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David T. Blaauw:
Robust SAT-Based Search Algorithm for Leakage Power Reduction. 167-177
Timing
- Kyu-won Choi, Abhijit Chatterjee:
PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI. 178-187 - Daniel González, Antonio García, Graham A. Jullien, Javier Ramírez, Luis Parrilla, Antonio Lloris-Ruíz:
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems. 188-197 - Mario R. Casu
Clock Distribution Network Optimization under Self-Heating and Timing Constraints. 198-208 - Raúl Jiménez, Pilar Parra Fernández
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. 209-218
Gate-Level Modeling
- José Luis Rosselló, Jaume Segura
A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers. 219-228 - Spiridon Nikolaidis, Haroula Pournara, Alexander Chatzigeorgiou:
Output Waveform Evaluation of Basic Pass Transistor Structure. 229-238 - Massimo Alioto, Gaetano Palumbo, Massimo Poli:
An Approach to Energy Consumption Modeling in RC Ladder Circuits. 239-246 - Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Structure Independent Representation of Output Transition Time for CMOS Library. 247-257
Memory Optimization
- Murali Jayapala, Francisco Barat, Pieter Op de Beeck, Francky Catthoor, Geert Deconinck
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors. 258-267 - Xuemei Zhao, Yizheng Ye:
Design and Realization of a Low Power Register File Using Energy Model. 268-277 - Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga:
Register File Energy Reduction by Operand Data Reuse. 278-288 - Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose:
Energy-Efficient Design of the Reorder Buffer. 289-299
High-Level Modeling and Design
- Kiyoo Itoh:
Trends in Ultralow-Voltage RAM Technology. 300-313 - Luca Benini, Alberto Macii
Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems. 314-322 - Nikolaos D. Zervas, G. Pagkless, Minas Dasygenis, Dimitrios Soudris
Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors. 323-331 - Eric Senn, Nathalie Julien, Johann Laurent, Eric Martin:
Power Consumption Estimation of a C Program for Data-Intensive Applications. 332-341
Communications Modeling and Activity Reduction
- Claudia Kretzschmar, Robert Siegmund, Dietmar Müller:
A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission. 342-352 - Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. 353-362 - Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo:
Low-Power FSMs in FPGA: Encoding Alternatives. 363-370 - Alejandro Linares-Barranco, Gabriel Jiménez, Antón Civit, Bernabé Linares-Barranco:
Synthetic Generation of Events for Address-Event-Representation Communications. 371-379
Posters
- Toshinori Sato, Itsujiro Arita:
Reducing Energy Consumption via Low-Cost Value Prediction. 380-389 - Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin:
Dynamic Voltage Scheduling for Real Time Asynchronous Systems. 390-399 - Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. 400-408 - Kostas Masselos, Panagiotis Merakos, Constantinos E. Goutis:
Power Efficient Vector Quantization Design Using Pixel Truncation. 409-418 - Artur Wróblewski, Florian Auernhammer, Josef A. Nossek:
Minimizing Spurious Switching Activities in CMOS Circuits. 419-428 - Massimo Alioto, Gaetano Palumbo:
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates. 429-437 - Gregorio Cappuccino, Giuseppe Cocorullo:
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines. 438-447 - Pilar Parra Fernández
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. 448-457 - Achim Freimann:
Probabilistic Power Estimation for Digital Signal Processing Architectures. 458-467 - Rosario Mita, Gaetano Palumbo:
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input. 468-476 - Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). 477-486 - Razvan Ionita, Andrei Vladimirescu, Paul G. A. Jespers:
Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems. 487-494
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