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Bertrand Hochet
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2000 – 2009
- 2009
- [c5]Vasanth Iyer
, S. Sitharama Iyengar, Garimella Rama Murthy, Bertrand Hochet, Vir V. Phoha
Multi-hop scheduling and local data link aggregation dependant Qos in modeling and simulation of power-aware wireless sensor networks. IWCMC 2009: 844-848 - 2002
- [e1]Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido:
Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002. Lecture Notes in Computer Science 2451, Springer 2002, ISBN 3-540-44143-3 [contents]
1990 – 1999
- 1999
- [c4]François Kaess, Riad Kanan
Performance/power tradeoffs in high-speed GaAs ADCs. ISCAS (2) 1999: 322-325 - 1996
- [j4]Riad Kanan
Pseudo-complementary FET logic (PCFL): a low-power logic family in GaAs. IEEE J. Solid State Circuits 31(7): 992-1000 (1996) - 1994
- [j3]Patrick Thiran, Vincent Peiris, Pascal Heim, Bertrand Hochet:
Quantization effects in digitally behaving circuit implementations of Kohonen networks. IEEE Trans. Neural Networks 5(3): 450-458 (1994) - 1991
- [c3]Guy Corbaz, Jean Duprat, Bertrand Hochet, Jean-Michel Muller
Implementation of a VLSI polynomial evaluator for real-time applications. ASAP 1991: 13-24
1980 – 1989
- 1989
- [j2]Bertrand Hochet, Patrice Quinton, Yves Robert
Systolic Gaussian Elimination over GF(p) with Partial Pivoting. IEEE Trans. Computers 38(9): 1321-1324 (1989) - 1987
- [j1]Alain Guyot, Bertrand Hochet, Jean-Michel Muller:
A Way to Build Efficient Carry-Skip Adders. IEEE Trans. Computers 36(10): 1144-1152 (1987) - [c2]Michel Cosnard, Alain Guyot, Bertrand Hochet, Jean-Michel Muller
The FELIN arithmetic coprocessor chip. IEEE Symposium on Computer Arithmetic 1987: 107-112 - [c1]Bertrand Hochet, Patrice Quinton, Yves Robert
Systolic solution of linear systems over GF(p) with partial pivoting. IEEE Symposium on Computer Arithmetic 1987: 161-168
Coauthor Index
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