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1st LATW 2000: Rio de Janeiro, RJ, Brazil
- 1st Latin American Test Workshop, LATW 2000, Rio de Janeiro, RJ, Brazil, March 13-15, 2000. IEEE 2000
- Margrit Reni Krug, Marcelo Lubaszewski, José Manuel Martins Ferreira, Gustavo Ribeiro da Costa Alves:
Implementing a Self-Checking PROFIBUS Slave. LATW 2000: 4-8 - Jose Artur Quilici González, José Roberto de A. Amazonas, Marius Strum, Wang Jiang Chau:
Self Test Built-in Plan for Data-Path Functional Units. LATW 2000: 9-14 - Fernanda Gusmão de Lima, Eduardo D'Avila, Mauricio Moraes, Marcelo Lubaszewski, Ricardo Reis:
A Self-Testing Mask Programmable Matrix Using Built-in Current Sensing. LATW 2000: 15-19 - Helano S. Castro, Regis C. de Araujo, Giovanni C. Barroso:
FTRT_OS - A Fault-Tolerant Operating System for Real-Time Applications: An Experience with Digital Signal Processor (DSP) Architecture. LATW 2000: 22-28 - Fabian Vargas, Alexandre M. Amory, Raoul Velazco:
Fault-Tolerance in VHDL Description: Transient-Fault Injection & Early Reliability Estimation. LATW 2000: 29-35 - Ph. Cheynet, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Hardening the Software with Respect to Transient Errors: a Method and Experimental Results. LATW 2000: 36-40 - Min-Hsing P. Chen, André Ivanov, Sassan Tabatabaei:
Defect Oriented Testing of an ECL/CMOS Level Converter Circuit. LATW 2000: 42-46 - Antonio Zenteno, Víctor H. Champac, Joan Figueras:
Detectability Dependency on Test Generation Process for Interconnection Opens. LATW 2000: 47-53 - Rodrigo Picos, J. Colom, Miquel Roca, Eugeni Isern, Jaume Segura, Oscar Calvo, Eugenio García-Moreno:
Transient Current Monitoring Using a Current-to-Frequency Converter. LATW 2000: 54-58 - Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone:
Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits. LATW 2000: 59-64 - Marcelino B. Santos, João Paulo Teixeira:
Experiments on RTL ATPG and Fault Simulation for High Defect Coverage in Digital Systems-on-a-Chip. LATW 2000: 66-71 - Jayanta Batra, Magdy S. Abadir, Jacob A. Abraham:
A Quick and Inexpensive Method to Identify False Critical Paths Using ATPG Techniques: an Experiment with a PowerPC Microprocessor. LATW 2000: 72-76 - Rolf Drechsler, Wolfgang Günther, Bernd Becker:
Testability of Circuits Derived from Lattice Diagrams. LATW 2000: 77-81 - José Vicente Calvano, Vladimir Castro Alves, Marcelo Soares Lubaszewski:
Mixed-Signal Test Bus IEEE 1149.4 Compatible BIST Scheme for Classical 2nd Order Filter Approximations using the Transient Response Analysis Method. LATW 2000: 84-87 - Luigi Carro, Michel Renovell, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs:
On the Temperature Dependencies of Analog BIST. LATW 2000: 88-93 - Mihalis Psarakis, Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
Deterministic Built-In Self -Test for Shifters, Adders and ALUs in Datapaths. LATW 2000: 98-103 - S. Caceres, J. M. Ruiz, F. A. Trelles, J. A. Domingues, S. de Pablo:
On the Study of a New BIST Technique Using Reseeding of Linear Feedback Shift Register toAccelerate the Test. LATW 2000: 104-109 - Peter Bukovjan, Laurent Ducerf-Bourbon, Meryem Marzouki:
Cost/Quality Trade-Off in Synthesis for BIST. LATW 2000: 110-115 - Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
Minimizing the Hardware Overhead of a Histogram-Based BIST Scheme for Analog-to-Digital Converters. LATW 2000: 118-122 - Eduardo J. Peralías, Adoración Rueda, José L. Huertas:
Alternative DFT Strategies for High-Speed Pipelined Data Converters. LATW 2000: 123-127 - Sule Ozev, Alex Orailoglu:
Block-Based Test Integration for Analog Integrated Circuits. LATW 2000: 128-132 - Érika F. Cota, Marcelo Lubaszewski, Raoul Velasco, Sana Rezgui:
Synthesis of a 8051-Like Microcontroller Tolerant to Transient Faults. LATW 2000: 134-139 - Jorge Marcos, Ana Gomez, Enrique Mandado, Carlos Peñalver, Alfonso Lago:
Fail-Safe and Test for Electronic Control Systems Using PLCs. LATW 2000: 140-145 - Eduardo Bezerra, Fabian Vargas, Michael Paul Gough:
Merging BIST and Configurable Computing Technology to Improve Availability in Space Applications. LATW 2000: 146-151 - Alessandro Brawerman, Elias P. Duarte Jr.:
A Synchronous Testing Strategy for Hierarchical Adaptive Distributed System-Level Diagnosis. LATW 2000: 154-161 - Antonio Caruso, Stefano Chessa, Piero Maestrini, Paolo Santi:
Reliable Diagnosis of Grid-Connected Systems. LATW 2000: 162-165 - Jadson Igor Siqueira, Eduardo Fabris, Elias P. Duarte Jr.:
A Token-Based Testing Strategy for Non-Broadcast Network Diagnosis. LATW 2000: 166-171 - Gary W. Maier, Shawn Smith:
Electronic Process Limited Yield. LATW 2000: 174-180 - Victor Sonnenberg, João Antonio Martino:
Determination of Silicon Film Thickness in SOI Capacitors. LATW 2000: 181-184 - José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski:
The Use of Macromodels on Op-Amp Circuits Fault Modeling. LATW 2000: 188-192 - Jaime Velasco-Medina, Iyad Rayane, Michael Nicolaidis:
On-Line BIST for Testing Analog Circuits. LATW 2000: 193-195 - Guillermo Espinosa Flores-Verdad, José Luis Vázquez-González:
RSM and Simplex Optimization for Parametric Fault Diagnosis of Analog Integrated Circuits. LATW 2000: 196-200 - Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test Configuration Generation for FPGA Logic Cells. LATW 2000: 202-208 - Luigi Carro, Luciano Agostini, Roberto Pacheco, Marcelo Lubaszewski:
Using Reconfigurability Features to Break Down Test Costs: a Case Study. LATW 2000: 209-214 - V. A. Zivkovic, Ronald J. W. T. Tangelder, H. G. Herkhoff:
The Test-Cycle Minimization in Parameterized Bus-Oriented Datapath Designs. LATW 2000: 215-220 - Leticia Mara Peres, Silvia Regina Vergilio, Mário Jino, José Carlos Maldonado:
Path Selection Strategies in the Context of Software Testing Criteria. LATW 2000: 222-227 - Silvia Regina Vergilio, José Carlos Maldonado, Mário Jino:
Constraint Based Criteria: An Approach for Test Case Selection in the Structural Testing. LATW 2000: 228-234 - Luiza de Macedo Mourelle, Nadia Nedjah:
Codesign System Modeling for Performance Analysis. LATW 2000: 235-242 - Andreas G. Veneris, Magdy S. Abadir, Ibrahim N. Haji:
Design Optimization Based on Diagnosis Techniques. LATW 2000: 244-249 - Yiorgos Makris, Alex Orailoglu:
Exploiting Off-Line Hierarchical Test Paths in Module Diagnosis and On-Line Test. LATW 2000: 250-255 - Zdenek Kotásek, Richard Ruzicka, Jan Hlavicka:
Formal Approach to the RTL Testability Analysis. LATW 2000: 256-261 - A. S. Nicolett, João A. Martino, E. Simoen, C. Claeys, Marcelo Bellodi, M. A. Pavanello:
A New Method to Extract the Silicon Film Thickness of Enhancement Mode Fully Depleted SOIN MOSFETs. LATW 2000: 264-267
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