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ISVLSI 2023: Foz do Iguacu, Brazil
- IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2023, Foz do Iguacu, Brazil, June 20-23, 2023. IEEE 2023, ISBN 979-8-3503-2769-4
- Deepak Puthal, Saraju P. Mohanty, Amit Kumar Mishra, Chan Yeob Yeun, Ernesto Damiani:
Revolutionizing Cyber Security: Exploring the Synergy of Machine Learning and Logical Reasoning for Cyber Threats and Mitigation. 1-6 - Elias de Almeida Ramos, Ricardo Reis:
Using Lyapunov Exponents and Entropy to Estimate Sensitivity to Process Variability. 1-6 - Arjun Suresh
, Siva Nishok Dhanuskodi, Daniel E. Holcomb:
A Secure Design Methodology to Prevent Targeted Trojan Insertion during Fabrication. 1-6 - Arthur Francisco Lorenzon, Guilherme Korol, Marcelo Brandalero, Antonio Carlos Schneider Beck:
Harnessing the Effects of Process Variability to Mitigate Aging in Cloud Servers. 1-6 - Yi Xiao, Yixin Xu, Shan Deng, Zijian Zhao, Sumitha George, Kai Ni, Vijaykrishnan Narayanan:
A Compact Ferroelectric 2T-(n+1)C Cell to Implement AND-OR Logic in Memory. 1-6 - Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory:
Formal Temporal Characterization of Register Vulnerability in Digital Circuits. 1-6 - Seema G. Aarella
Fortified-Edge 2.0: Machine Learning based Monitoring and Authentication of PUF-Integrated Secure Edge Data Center. 1-6 - Prabhu Vellaisamy, Harideep Nair
tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit. 1-6 - Omkar G. Ratnaparkhi, Madhav Rao:
CWAHA: Cluster-Wise Approximation for Hardware implementation of Arithmetic functions. 1-6 - Geancarlo Abich
Power, Performance and Reliability Evaluation of Multi-thread Machine Learning Inference Models Executing in Multicore Edge Devices. 1-6 - Sundarakumar Muthukumaran, Aparajithan Nathamuni Venkatesan, Kishore Pula, Ram Venkat Narayanan, Ranga Vemuri, John Marty Emmert:
Reverse Engineering of RTL Controllers from Look-Up Table Netlists. 1-6 - Leonardo Heitich Brendler, Hervé Lapuyade, Yann Deval, Ricardo Reis, François Rivet:
A MCU-robust Interleaved Data/Detection SRAM for Space Environments. 1-6 - Sajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler:
LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing. 1-6 - Marcello M. Muñoz, Denis Maass, Murilo R. Perleberg
Efficient Hardware Design for the VVC Affine Motion Compensation Exploiting Multiple Constant Multiplication. 1-6 - Joy Dutta
IoMT Synthetic Cardiac Arrest Dataset for eHealth with AI-based Validation. 1-6 - Changfu He, Keyue Deng, Suwen Song, Zhongfeng Wang:
Column-Weighted Probabilistic GDBF Decoder for Irregular LDPC Codes. 1-6 - Tiago da Silva Almeida, Lucas Wanner:
Efficient Accelerator Design in High-Level Synthesis Using Approximate Logic Components. 1-6 - Sachin Bhat, Sourabh Kulkarni, Csaba Andras Moritz:
Compact Model Parameter Extraction using Bayesian Machine Learning. 1-6 - Julio Costella Vicenzi, Guilherme Korol, Michael Guilherme Jordan, Wagner Ourique de Morais, Hazem Ali
Dynamic Offloading for Improved Performance and Energy Efficiency in Heterogeneous IoT-Edge-Cloud Continuum. 1-6 - Nidhi Anantharajaiah, Yunhe Xu, Fabian Lesniak, Tanja Harbaum
DREAM: Distributed Reinforcement Learning Enabled Adaptive Mixed-Critical NoC. 1-6 - Hui Wang, Jinming Lu, Jun Lin, Zhongfeng Wang:
An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd. 1-6 - Trishna Rajkumar:
Exploiting Routing Asymmetry for APUF Implementation in FPGA: A Proof-of-Concept. 1-4 - Prashanth H. C., Prashanth Jonna, Madhav Rao:
CellFlow: Automated Standard Cell Design Flow. 1-5 - Vishu Saxena, Yash Jain, Sparsh Mittal:
Machine Learning and Polynomial Chaos models for Accurate Prediction of SET Pulse Current. 1-6 - Venkata K. V. V. Bathalapalli
iTPM: Exploring PUF-based Keyless TPM for Security-by-Design of Smart Electronics. 1-6 - S. N. Raghava, Prashanth H. C., Bindu G. Gowda
Design-Space Exploration of Multiplier Approximation in CNNs. 1-6 - Baiqing Zhong, Mingyu Wang, Chuanghao Zhang, Yangzhan Mai, Xiaojie Li, Zhiyi Yu:
A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN Inference. 1-6 - Anand Menon, Amisha Srivastava, Shamik Kundu, Kanad Basu:
Application Profiling Using Register-Instruction Hardware Performance Counters. 1-6 - Marcel Walter
Versatile Signal Distribution Networks for Scalable Placement and Routing of Field-coupled Nanocomputing Technologies. 1-6 - Raphael Cardoso, Clément Zrounba, Mohab Abdalla, Paul Jiménez, Mauricio Gomes de Queiroz, Benoît Charbonnier, Fabio Pavanello, Ian O'Connor, Sébastien Le Beux:
Photonic Convolution Engine Based on Phase-Change Materials and Stochastic Computing. 1-6 - Shams Tarek, Hasan Al Shaikh, Sree Ranjani Rajendran, Farimah Farahmandi:
Benchmarking of SoC-Level Hardware Vulnerabilities: A Complete Walkthrough. 1-6 - Sadia Anjum Tumpa, Sonali Singh, Md Fahim Faysal Khan
Federated Learning with Spiking Neural Networks in Heterogeneous Systems. 1-6 - Hongtao Zhong, Yu Zhu, Longfei Luo, Taixin Li, Chen Wang, Yixin Xu, Tianyi Wang, Yao Yu, Vijaykrishnan Narayanan, Yongpan Liu, Liang Shi, Huazhong Yang, Xueqing Li:
Fe-GCN: A 3D FeFET Memory Based PIM Accelerator for Graph Convolutional Networks. 1-6 - Grant Brown, Ganesh Gore, Pierre-Emmanuel Gaillardon:
Performance Optimized Clock Tree Embedding for Auto-Generated FPGAs. 1-6 - Taixin Li, Hongtao Zhong, Sumitha George, Vijaykrishnan Narayanan, Liang Shi, Huazhong Yang, Xueqing Li:
Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays. 1-6 - Indranee Kashyap, Dipika Deb, Nityananda Sarma:
Grep: Performance Enhancement in MultiCore Processors using an Adaptive Graph Prefetcher. 1-6 - Harshita Gupta, Mayank Kabra, Asmita Zjigyasu, Madhav Rao:
FastNTT: Design and Evaluation of Modular-Reduction Based Fast NTT Design on FPGA. 1-6 - Michael Guilherme Jordan, Guilherme Korol, Tiago Knorst, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
Resource Provisioning for CPU-FPGA Environments with Adaptive HLS-Versioning and DVFS. 1-6 - Ruan Evangelista Formigoni, Ricardo S. Ferreira, Omar P. Vilela Neto, José Augusto Miranda Nacif:
L-BANCS: A Multi-Phase Tile Design for Nanomagnetic Logic. 1-6 - Gabriel Ammes, Paulo F. Butzen
Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis. 1-6 - Guilherme Korol, Michael Guilherme Jordan, Mateus Beck Rutzig, Jerónimo Castrillón, Antonio Carlos Schneider Beck:
Design Space Exploration for CNN Offloading to FPGAs at the Edge. 1-6 - Yerzhan Mustafa
Modeling and Analysis of Switched-Capacitor Converters as a Multi-port Network for Covert Communication. 1-6 - Giani Augusto Braga, Marcio M. Gonçalves, José Rodrigo Azambuja:
Evaluating an XOR-based Hybrid Fault Tolerance Technique to Detect Faults in GPU Pipelines. 1-6 - Chunkai Fu, Ben Trombley, Hua Xiang, Gi-Joon Nam, Jiang Hu:
Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops. 1-6 - Priyanka Panigrahi, Chandan Karfa:
An Investigation into the Security of Register Allocation with Spilling and Splitting. 1-6 - Sobhan Niknam, Yixian Shen
3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems. 1-6 - Vedika Saravanan, Mohammad Walid Charrwi, Samah Mohamed Saeed:
Revisiting Trojan Insertion Techniques for Post-Silicon Trojan Detection Evaluation. 1-6 - Rodrigo N. Wuerdig, Vitor Hugo F. Maciel, Ricardo Reis, Sergio Bampi:
LEX - A Cell Switching Arcs Extractor: A Simple SPICE-Input Interface for Electrical Characterization. 1-6 - Ivan Saraiva Silva, Francisco Carlos Silva Junior:
X4-RARE: Revisiting the X4CP32 Coarse-Grained Reconfigurable Architecture Model. 1-6 - Alessandro Nadalini, Georg Rutishauser, Alessio Burrello, Nazareno Bruschi, Angelo Garofalo, Luca Benini, Francesco Conti, Davide Rossi:
A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks. 1-6 - Sanampudi Gopala Krishna Reddy, Gogireddy Ravi Kiran Reddy, D. R. Vasanthi, Madhav Rao:
Design and Evaluation of M-Term Non-Homogeneous Hybrid Karatsuba Polynomial Multiplier. 1-6 - Kamal Danouchi
Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits. 1-6
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