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Tanja Harbaum
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2020 – today
- 2024
- [c41]Tanja Harbaum, Alexey Serdyuk, Fabian Kreß, Tim Hamann, Jens Barth, Peter Kämpf, Florent Imbert, Yann Soullard, Romain Tavenard, Éric Anquetil, Jessica Delahaie:
KIHT: Kaligo-Based Intelligent Handwriting Teacher. DATE 2024: 1-6 - [c40]Patrick Schmidt, Iuliia Topko, Matthias Stammler, Tanja Harbaum, Jürgen Becker, Rico Berner, Omar Ahmed, Jakub Jagielski, Thomas Seidler, Markus Abel, Marius Kreutzer, Maximilian Kirschner, Victor Pazmino Betancourt, Robin Sehm, Lukas Groth, Andrija Neskovic, Rolf Meyer, Saleh Mulhem, Mladen Berekovic, Matthias Probst, Manuel Brosch, Georg Sigl, Thomas Wild, Matthias Ernst, Andreas Herkersdorf, Florian Aigner, Stefan Hommes, Sebastian Lauer, Maximilian Seidler, Thomas Raste, Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Muhammad Hassan, Albrecht Mayer:
EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge. DATE 2024: 1-6 - [c39]Julian Höfer, Matthias Stammler, Fabian Kreß, Tim Hotfilter, Tanja Harbaum, Jürgen Becker:
BayWatch: Leveraging Bayesian Neural Networks for Hardware Fault Tolerance and Monitoring. DFT 2024: 1-6 - [c38]Fabian Kreß, Vladimir Sidorenko, Iuliia Topko, Kai Lukas Unger, Tanja Harbaum, Jürgen Becker:
VHDL Crash Course: A Multimedia-Based Teaching Approach. GeCon 2024: 1-6 - [c37]Fabian Lesniak
, Annina Gutermann
Enhanced Accelerator Design for Efficient CNN Processing with Improved Row-Stationary Dataflow. ACM Great Lakes Symposium on VLSI 2024: 151-157 - [c36]Julian Höfer, Michael Gauß, Manuela Adams, Fabian Kreß, Fabian Kempf, Christian Maximilian Karle, Tanja Harbaum, Andreas Barth, Jürgen Becker:
A Challenge-Based Blended Learning Approach for an Introductory Digital Circuits and Systems Course. ISCAS 2024: 1-5 - [c35]Fabian Kreß, El Mahdi El Annabi, Tim Hotfilter, Julian Höfer, Tanja Harbaum, Jürgen Becker:
Automated Deep Neural Network Inference Partitioning for Distributed Embedded Systems. ISVLSI 2024: 39-44 - [c34]Matthias Stammler, Julian Höfer, Patrick Schmidt, Tanja Harbaum, Jürgen Becker:
ICE TEA: Insertion of Custom Early Exits for Time-, Energy- & Anomaly-Aware Neural Networks. ISVLSI 2024: 656-660 - [c33]Iuliia Topko, Tanja Harbaum, Jürgen Becker:
Towards a General Compilation Approach for On-device Training in Embedded Systems. NorCAS 2024: 1-7 - [c32]Christian Maximilian Karle, Marc Neu, Benjamin Nuss, Jiayi Chen, Lukas Witte, Andre Scheder, Tanja Harbaum, Jürgen Becker:
Modular Hardware Design for High-Performance MIMO-Capable SDR Systems to Accelerate 6G Development. SOCC 2024: 1-6 - [c31]Christian Maximilian Karle, Marc Neu, Benjamin Nuss, Lukas Witte, Andre Scheder, Eva Waldner, Ema Shkurtaj, Tanja Harbaum, Jürgen Becker:
Scalable Multi-Level Synchronization Technique of Distributed Multi-RFSoC-Server Systems for 6G. SOCC 2024: 1-6 - [c30]Jann Krausse, Moritz Neher, Iris Fürst-Walter, Carmen Weigelt, Tanja Harbaum, Klaus Knobloch, Jürgen Becker:
On Metric-Driven Development of Embedded Neuromorphic AI. SOCC 2024: 1-6 - [c29]Marc Neu, Christian Maximilian Karle, Patrick Schmidt, Julian Höfer, Tanja Harbaum, Jürgen Becker:
A Dynamically Pipelined Dataflow Architecture for Graph Convolutions in Real-Time Event Interpretation. SOCC 2024: 1-6 - [c28]Patrick Schmidt, Johannes Pfau, Tim Hotfilter, Matthias Stammler, Tanja Harbaum, Jürgen Becker:
RVVe: A Minimal RISC-V Vector Processor for Embedded AI Acceleration. SOCC 2024: 1-6 - [c27]Fabian Kreß, Alexey Serdyuk, Denis Kobsar, Tim Hotfilter, Julian Höfer, Tanja Harbaum, Jürgen Becker:
LOTTA: An FPGA-based Low-Power Temporal Convolutional Network Hardware Accelerator. SOCC 2024: 126-131 - [e3]Diana Göhringer, Uwe Gäbler, Tanja Harbaum, Klaus Hofmann:
37th IEEE International System-on-Chip Conference, SOCC 2024, Dresden, Germany, September 16-19, 2024. IEEE 2024, ISBN 979-8-3503-7756-9 [contents] - [i2]Fabian Kreß, El Mahdi El Annabi, Tim Hotfilter, Julian Höfer, Tanja Harbaum, Jürgen Becker:
Automated Deep Neural Network Inference Partitioning for Distributed Embedded Systems. CoRR abs/2406.19913 (2024) - 2023
- [j1]Fabian Kreß
CNNParted: An open source framework for efficient Convolutional Neural Network inference partitioning in embedded systems. Comput. Networks 229: 109759 (2023) - [c26]Tim Hotfilter
A Hardware-Centric Approach to Increase and Prune Regular Activation Sparsity in CNNs. AICAS 2023: 1-5 - [c25]Fabian Kempf, Julian Höfer
The ZuSE-KI-Mobil AI Accelerator SoC: Overview and a Functional Safety Perspective. DATE 2023: 1-6 - [c24]Matthias Stammler, Matthias Hamann, Tanja Harbaum, Jürgen Becker:
Mitigating Masking in Automotive Communication Systems: Modeling and Hardware Generation. DSD 2023: 561-568 - [c23]Fabian Kreß, Alexey Serdyuk, Micha Hiegle, Disnebio Waldmann, Tim Hotfilter
ATLAS: An Approximate Time-Series LSTM Accelerator for Low-Power IoT Applications. DSD 2023: 569-576 - [c22]Julian Höfer
SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators. ACM Great Lakes Symposium on VLSI 2023: 287-292 - [c21]Fabian Lesniak
Non-Intrusive Runtime Monitoring for Manycore Prototypes. DroneSE/RAPIDO@HiPEAC 2023: 31-38 - [c20]Tim Hotfilter
An Analytical Model of Configurable Systolic Arrays to find the Best-Fitting Accelerator for a given DNN Workload. DroneSE/RAPIDO@HiPEAC 2023: 73-78 - [c19]Julian Höfer
A Hardware-Aware Sampling Parameter Search for Efficient Probabilistic Object Detection. ICVS 2023: 299-309 - [c18]Matthias Stammler
EFFECT: An End-to-End Framework for Evaluating Strategies for Parallel AI Anomaly Detection. INNS DLIA@IJCNN 2023: 499-508 - [c17]Iris Fürst-Walter
Design Space Exploration on Efficient and Accurate Human Pose Estimation from Sparse IMU-Sensing. IROS 2023: 10888-10893 - [c16]Nidhi Anantharajaiah, Yunhe Xu, Fabian Lesniak, Tanja Harbaum
DREAM: Distributed Reinforcement Learning Enabled Adaptive Mixed-Critical NoC. ISVLSI 2023: 1-6 - [c15]Nidhi Anantharajaiah, Fabian Lesniak, Tanja Harbaum, Jürgen Becker:
Reinforcement Learning Enabled Multi-Layered NoC for Mixed Criticality Systems. MCSoC 2023: 38-44 - [c14]Fabian Lesniak
Low-latency inter-domain communication on the Xen hypervisor. MCSoC 2023: 340-346 - [c13]Fabian Kreß, Johannes Pfau
Automated Replacement of State-Holding Flip-Flops to Enable Non-Volatile Checkpointing. NorCAS 2023: 1-7 - [c12]Tim Hotfilter
Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy Efficiency. SOCC 2023: 1-6 - [c11]Fabian Lesniak
Approximate Accelerators: A Case Study using Runtime Reconfigurable Processors. SOCC 2023: 1-6 - [c10]Alexey Serdyuk, Fabian Kreß, Micha Hiegle, Tanja Harbaum, Jürgen Becker, Florent Imbert, Yann Soullard, Romain Tavenard, Éric Anquetil, Jens Barth, Peter Kämpf:
Towards the on-device Handwriting Trajectory Reconstruction of the Sensor Enhanced Pen. WF-IoT 2023: 1-6 - [e2]Jürgen Becker, Andrew Marshall, Tanja Harbaum, Amlan Ganguly, Fahad Siddiqui, Kieran McLaughlin:
36th IEEE International System-on-Chip Conference, SOCC 2023, Santa Clara, CA, USA, September 5-8, 2023. IEEE 2023, ISBN 979-8-3503-0011-6 [contents] - [i1]Iris Fürst-Walter, Antonio Nappi, Tanja Harbaum, Jürgen Becker:
Design Space Exploration on Efficient and Accurate Human Pose Estimation from Sparse IMU-Sensing. CoRR abs/2308.02397 (2023) - 2022
- [c9]Fabian Kreß
Hardware-aware Partitioning of Convolutional Neural Network Inference for Embedded AI Applications. DCOSS 2022: 133-140 - [c8]Fabian Kreß
Hardware-aware Workload Distribution for AI-based Online Handwriting Recognition in a Sensor Pen. MECO 2022: 1-4 - [c7]Fabian Kreß
Automated Search for Deep Neural Network Inference Partitioning on Embedded FPGA. PKDD/ECML Workshops (1) 2022: 557-568 - [c6]Fabian Kempf, Julian Höfer
Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors. SOCC 2022: 1-6 - [e1]Sakir Sezer, Thomas Büchner, Jürgen Becker, Andrew Marshall, Fahad Siddiqui, Tanja Harbaum, Kieran McLaughlin:
35th IEEE International System-on-Chip Conference, SOCC 2022, Belfast, United Kingdom, September 5-8, 2022. IEEE 2022, ISBN 978-1-6654-5985-3 [contents]
2010 – 2019
- 2019
- [c5]Johannes Pfau
A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s. SoCC 2019: 294-299 - 2018
- [c4]Tanja Harbaum
A Content - Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique. SoCC 2018: 206-212 - 2017
- [c3]Tanja Harbaum
Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration. SoCC 2017: 153-158 - 2016
- [c2]Tanja Harbaum
A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment. FCCM 2016: 184-191 - 2013
- [c1]Carsten Tradowsky, Tanja Harbaum
LImbiC: An adaptable architecture description language model for developing an application-specific image processor. ISVLSI 2013: 34-39
Coauthor Index
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last updated on 2024-12-03 20:30 CET by the dblp team
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