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24th FPL 2014: Munich, Germany
- 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014. IEEE 2014
- Frederik Grüll, Udo Kebschull:
Biomedical image processing and reconstruction with dataflow computing on FPGAs. 1-2 - Zhuo Qian, Nasibeh Nasiri, Oren Segal, Martin Margala
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FPGA implementation of low-power split-radix FFT processors. 1-2 - Thinh Hung Pham
Efficient multi-standard cognitive radios on FPGAs. 1-2 - Marlon Wijeyasinghe, David Thomas:
Using high-level knowledge to enhance data channels in FPGA streaming systems. 1-2 - Dominik Sondej
A combination of multi-edge coding and independent coding lines for time-to-digital conversion. 1-2 - Marcin Pietras:
Hardware conversion of neural networks simulation models for neural processing accelerator implemented as FPGA-based SoC. 1-4 - Alexander Wild, Tim Güneysu
Enabling SRAM-PUFs on Xilinx FPGAs. 1-4 - Shyamsundar Venkataraman, Rui Santos, Anup Das
A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs. 1-4 - Ali Ebrahim
A fast and scalable FPGA damage diagnostic service for R3TOS using BIST cloning technique. 1-4 - Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise:
Ultrasmall: The smallest MIPS soft processor. 1-4 - Aiko Iwasaki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa:
A soft-core processor for finite field arithmetic with a variable word size accelerator. 1-4 - Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri:
Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy. 1-4 - Abdulazim Amouri, Florent Bruguier
Aging effects in FPGAs: an experimental analysis. 1-4 - Wilson José, Ana Rita Silva, Horácio C. Neto
Efficient implementation of a single-precision floating-point arithmetic unit on FPGA. 1-4 - Cláudio Machado Diniz, Muhammad Shafique
Run-time accelerator binding for tile-based mixed-grained reconfigurable architectures. 1-4 - Unai Martinez-Corral
Scalable parallel architecture for singular value decomposition of large matrices. 1-4 - Juan Valverde, Alfonso Rodríguez, Julio Camarero, Andrés Otero
A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. 1-4 - Eugene Cartwright, Alborz Sadeghian, Sen Ma, David Andrews
Achieving portability and efficiency over chip heterogeneous multiprocessor systems. 1-4 - Muhammed Al Kadi, Max Ferger, Volker Stegemann, Michael Hübner:
Multi-FPGA reconfigurable system for accelerating MATLAB simulations. 1-4 - Tassadaq Hussain, Oscar Palomar
MAPC: Memory access pattern based controller. 1-4 - Hock Soon Low, Delong Shang, Fei Xia, Alexandre Yakovlev
Asynchronously assisted FPGA for variability. 1-4 - Fabio Garzia, Alexander Rügamer, Robert Koch, Philipp Neumaier, Ekaterina Serezhkina, Matthias Overbeck, Günter Rohmer:
Experimental multi-FPGA GNSS receiver platform. 1-4 - Fumito Yamaguchi, Kanae Matsui, Hiroaki Nishi
RAM-based hardware accelerator for network data anonymization. 1-4 - Siddhartha, Nachiket Kapre:
Heterogeneous dataflow architectures for FPGA-based sparse LU factorization. 1-4 - Alexandru Amaricai, Constantina-Elena Gavriliu, Oana Boncalo:
An FPGA sliding window-based architecture harris corner detector. 1-4 - Yanbiao Li, Dafang Zhang, Xian Yu, Wei Liang
Accelerate NDN name lookup using FPGA: Challenges and a scalable approach. 1-4 - Youkou Sogabe, Tsutomu Maruyama:
FPGA acceleration of short read mapping based on sort and parallel comparison. 1-4 - Kenji Kanazawa, Tsutomu Maruyama:
FPGA acceleration of SAT/Max-SAT solving using variable-way cache. 1-4 - Michael Kunz, Alexander Ostrowski, Peter Zipf
An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications. 1-4 - Bogdan Pasca
Low-cost multiplier-based FPU for embedded processing on FPGA. 1-4 - Tim Güneysu
THOR - The hardware onion router. 1-4 - Pablo Leyva, Ginés Doménech-Asensi, F. Javier Garrigós
Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm. 1-4 - Dajung Lee, Janarbek Matai, Brad T. Weals, Ryan Kastner
High throughput channel tracking for JTRS wireless channel emulation. 1-4 - Jinzhe Yang, Binghuan Lin, Wayne Luk, Terence Nahar:
Particle filtering-based Maximum Likelihood Estimation for financial parameter estimation. 1-4 - Hasan Azgin, Serkan Yaliman, Ilker Hamzaoglu:
A high performance alternating projections image demosaicing hardware. 1-4 - Muhuan Huang, Kevin Lim, Jason Cong:
A scalable, high-performance customized priority queue. 1-4 - Lei Xu
Privacy preserving large scale DNA read-mapping in MapReduce framework using FPGAs. 1-4 - Arash Farhadi Beldachi, José L. Núñez-Yáñez
Accurate power control and monitoring in ZYNQ boards. 1-4 - Igor Villata, Unai Bidarte
Fast and accurate SEU-tolerance characterization method for Zynq SoCs. 1-4 - Luca Gallo, Alessandro Cilardo, David B. Thomas, Samuel Bayliss, George A. Constantinides:
Area implications of memory partitioning for high-level synthesis on FPGAs. 1-4 - Fatemeh Eslami, Steven J. E. Wilton:
Incremental distributed trigger insertion for efficient FPGA debug. 1-4 - Bajaj Ronak, Suhaib A. Fahmy
Efficient mapping of mathematical expressions into DSP blocks. 1-4 - Siqi Wang
Leakage and performance aware resource management for 2D dynamically reconfigurable FPGA architectures. 1-4 - Brandon Kyle Hamilton, Michael Inggs
Mixed-architecture process scheduling on tightly coupled reconfigurable computers. 1-4 - Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez:
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. 1-4 - Adithya Pulli, Carlo Galuzzi, Georgi Gaydadjiev
Towards domain-specific Instruction-Set Generation. 1-4 - Moritz Schmid, Nicolas Apelt, Frank Hannig
An image processing library for C-based high-level synthesis. 1-4 - Matthew Naylor, Simon W. Moore
Rapid codesign of a soft vector processor and its compiler. 1-4 - Gorker Alp Malazgirt, Hasan Erdem Yantir, Arda Yurdakul, Smaïl Niar:
Application specific multi-port memory customization in FPGAs. 1-4 - Ryan Marlow, Chris Dobson, Peter Athanas:
An enhanced and embedded GNU radio flow. 1-4 - Jason Xin Zheng, Dongfang Li, Miodrag Potkonjak:
A secure and unclonable embedded system using instruction-level PUF authentication. 1-4 - Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Pattern-based FPGA logic block and clustering algorithm. 1-4 - Henry Block, Tsutomu Maruyama:
An FPGA hardware acceleration of the indirect calculation of tree lengths method for phylogenetic tree reconstruction. 1-4 - Bouthaina Damak
A mixed integer linear programming approach for design space exploration in FPGA-based MPSoC. 1-4 - Jens Huthmann, Julian Oppermann, Andreas Koch:
Automatic high-level synthesis of multi-threaded hardware accelerators. 1-4 - Rehan Ahmed, Assem A. M. Bsoul, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas:
High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs. 1-4 - Nima Safari, Volker Mauer, Shahin Gheitanchi:
Methods for implementation of feedback loops in high speed FPGA applications. 1-4 - Keitaro Takizawa, Shunya Hosaka, Hiroshi Saito:
A design support tool set for asynchronous circuits with bundled-data implementation on FPGAs. 1-4 - Shinya Takamaeda-Yamazaki, Kenji Kise:
flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms. 1-4 - Nam Ho, Paul Kaufmann, Marco Platzner
A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. 1-4 - Toru Katagiri, Hideharu Amano:
A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technology. 1-4 - Chen Yang, Leibo Liu
Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor. 1-4 - Vincent Mirian, Paul Chow:
Using an OpenCL framework to evaluate interconnect implementations on FPGAs. 1-4 - Athanasios Stratikopoulos, Grigorios Chrysos, Ioannis Papaefstathiou
HPC-gSpan: An FPGA-based parallel system for frequent subgraph mining. 1-4 - Oren Segal, Martin Margala
High level programming framework for FPGAs in the data center. 1-4 - Lukas Kekely
Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring. 1-4 - Thomas B. Preußer, Rainer G. Spallek:
Ready PCIe data streaming solutions for FPGAs. 1-4 - Oliver Knodel
Educating hardware design - From primary school children to postgraduate engineers. 1-4 - Zhenzhi Wu, Dake Liu, Zheng Yang, Qingying Wang, Wei Zhou:
FPGA implementation of a multi-algorithm parallel FEC for SDR platforms. 1-6 - James J. Davis, Peter Y. K. Cheung:
Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration. 1-6 - Shyamsundar Venkataraman, Rui Santos, Sidharth Maheshwari, Akash Kumar
Multi-directional error correction schemes for SRAM-based FPGAs. 1-8 - Teng Xu, Miodrag Potkonjak:
Robust and flexible FPGA-based digital PUF. 1-6 - Abhinav Agarwal, Haitham Hassanieh
High-throughput implementation of a million-point sparse Fourier Transform. 1-6 - Umer I. Cheema, Gregory Nash, Rashid Ansari, Ashfaq A. Khokhar:
Power-efficient re-gridding architecture for accelerating Non-uniform Fast Fourier Transform. 1-6 - Khalid Javeed
Radix-4 and radix-8 booth encoded interleaved modular multipliers over general Fp. 1-6 - Pavel Burovskiy, Stephen Girdlestone, Craig Davies, Spencer J. Sherwin
Dataflow acceleration of Krylov subspace sparse banded problems. 1-6 - Nithin George, HyoukJoong Lee, David Novo, Tiark Rompf, Kevin J. Brown, Arvind K. Sujeeth, Martin Odersky, Kunle Olukotun, Paolo Ienne:
Hardware system synthesis from Domain-Specific Languages. 1-8 - Roland Dobai:
Evolutionary on-line synthesis of hardware accelerators for software modules in reconfigurable embedded systems. 1-6 - Davor Capalija, Tarek S. Abdelrahman:
Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays. 1-8 - Mohamad Najem, Pascal Benoit, Florent Bruguier
Method for dynamic power monitoring on FPGAs. 1-6 - Christian Brugger, Christian de Schryver
HyPER: A runtime reconfigurable architecture for monte carlo option pricing in the Heston model. 1-8 - Jian Gong, Tao Wang, Jiahua Chen, Haoyang Wu, Fan Ye, Songwu Lu, Jason Cong:
An efficient and flexible host-FPGA PCIe communication library. 1-6 - Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. 1-6 - Liqun Yang, Haigang Yang, Wei Li, Zhihua Li, Zhihong Huang, Colin Yu Lin:
A semi-supervised modeling approach for performance characterization of FPGA architectures. 1-6 - Lin Gan, Haohuan Fu, Chao Yang
A highly-efficient and green data flow engine for solving euler atmospheric equations. 1-6 - Matthias Pohl, Michael Schaeferling, Gundolf Kiefer:
An efficient FPGA-based hardware framework for natural feature extraction and related Computer Vision tasks. 1-8 - Gary C. T. Chow, Paul Grigoras, Pavel Burovskiy, Wayne Luk:
An efficient sparse conjugate gradient solver using a Beneš permutation network. 1-7 - Stefan Wonneberger, Max Kohler, Wojciech Derendarz, Thorsten Graf, Rolf Ernst:
Efficient 3D triangulation in hardware for dense structure-from-motion in low-speed automotive scenarios. 1-6 - Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf
Pipelined reconfigurable multiplication with constants on FPGAs. 1-6 - Soh Jun Jie, Nachiket Kapre:
Comparing soft and hard vector processing in FPGA-based embedded systems. 1-7 - Martin Kumm, Peter Zipf
Pipelined compressor tree optimization using integer linear programming. 1-8 - Jasmina Vasiljevic, Paul Chow:
Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use. 1-8 - Zhenghong Jiang, Colin Yu Lin, Liqun Yang, Fei Wang, Haigang Yang:
Exploring architecture parameters for dual-output LUT based FPGAs. 1-6 - Ghada Dessouky, Michael J. Klaiber, Donald G. Bailey
Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architectures. 1-8 - A. Theodore Markettos, Paul James Fox, Simon W. Moore
Interconnect for commodity FPGA clusters: Standardized or customized? 1-8 - Junyi Liu, Helfried Peyrl, Andreas Burg
FPGA implementation of an interior point method for high-speed model predictive control. 1-8 - Oana Boncalo, Alexandru Amaricai, Andrei Hera, Valentin Savin
Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing. 1-6 - Kenneth M. Zick, Sen Li, Matthew French:
High-precision self-characterization for the LUT burn-in information leakage threat. 1-6 - Rui Santos, Shyamsundar Venkataraman, Anup Das
Criticality-aware scrubbing mechanism for SRAM-based FPGAs. 1-8 - Hirak J. Kashyap, Ricardo Chaves
Secure partial dynamic reconfiguration with unsecured external memory. 1-7 - Ernesto Sánchez, Luca Sterpone
Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs. 1-6 - Farnaz Gharibian, Lesley Shannon, Peter Jamieson:
Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data. 1-6 - Christian Beckhoff, Dirk Koch, Jim Tørresen:
Portable module relocation and bitstream compression for Xilinx FPGAs. 1-8 - Christian Fobel, Gary William Grewal, Deborah Stacey
A scalable, serially-equivalent, high-quality parallel placement methodology suitable for modern multicore and GPU architectures. 1-8 - Rui Jia, Colin Yu Lin, Zhenhong Guo, Rui Chen
A survey of open source processors for FPGAs. 1-6 - Mário P. Véstias
Trends of CPU, GPU and FPGA for high-performance computing. 1-6 - Oriol Arcas-Abella
An empirical evaluation of High-Level Synthesis languages and tools for database acceleration. 1-8 - Syed M. A. H. Jafri, Guilermo Serrano, Masoud Daneshtalab, Naeem Abbas, Ahmed Hemani, Kolin Paul, Juha Plosila
TransPar: Transformation based dynamic Parallelism for low power CGRAs. 1-8 - Honlian Su, Yu Fujita, Hideharu Amano:
Body bias control for a coarse grained reconfigurable accelerator implemented with Silicon on Thin BOX technology. 1-6 - Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
Caching memcached at reconfigurable network interface. 1-6 - Kermin Fleming, Hsin-Jung Yang, Michael Adler, Joel S. Emer:
The LEAP FPGA operating system. 1-8 - Shane T. Fleming, David B. Thomas:
Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCs. 1-6 - Andrew Canis, Stephen Dean Brown, Jason Helge Anderson:
Modulo SDC scheduling with recurrence minimization in high-level synthesis. 1-8 - Dirk Koch, Christian Beckhoff:
Hierarchical reconfiguration of FPGAs. 1-8 - Tuan D. A. Nguyen, Akash Kumar
PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems. 1-6 - Marcin Rogawski, Ekawat Homsirikamol, Kris Gaj:
A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs. 1-8 - Christophe Huriaux
FPGA architecture support for heterogeneous, relocatable partial bitstreams. 1-6 - Joshua S. Monson, Brad L. Hutchings:
New approaches for in-system debug of behaviorally-synthesized FPGA circuits. 1-6 - Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson:
Source-level debugging for FPGA high-level synthesis. 1-8 - Eddie Hung, Tim Todman
Transparent insertion of latency-oblivious logic onto FPGAs. 1-8 - Jeffrey B. Goeders, Steven J. E. Wilton:
Effective FPGA debug for high-level synthesis generated circuits. 1-8 - Pingfan Meng, Matthew Jacobsen, Motoki Kimura, Vladimir Dergachev, Thomas Anantharaman, Michael Requa, Ryan Kastner
Hardware accelerated novel optical de novo assembly for large-scale genomes. 1-8 - Raphael Polig, Kubilay Atasu
Compiling text analytics queries to FPGAs. 1-6 - Liucheng Guo, David B. Thomas, Ce Guo, Wayne Luk:
Automated framework for FPGA-based parallel genetic algorithms. 1-7 - Andreas Becher
Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration. 1-8 - Mohammad Hosseinabady
Run-time power gating in hybrid ARM-FPGA devices. 1-6 - Ali Ahari, Behnam Khaleghi, Zahra Ebrahimi
Towards dark silicon era in FPGAs using complementary hard logic design. 1-6 - Matthew Jacobsen, Siddarth Sampangi, Yoav Freund, Ryan Kastner
Improving FPGA accelerated tracking with multiple online trained classifiers. 1-7 - Wenlai Zhao, Haohuan Fu, Guangwen Yang, Wayne Luk:
Patra: Parallel tree-reweighted message passing architecture. 1-6 - Kizheppatt Vipin
DyRACT: A partial reconfiguration enabled accelerator and test platform. 1-7
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