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Jan Korenek
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2020 – today
- 2024
- [c76]Tomás Martínek, Jan Korenek, Tomás Cejka:
LGBM2VHDL: Mapping of LightGBM Models to FPGA. FCCM 2024: 97-103 - 2023
- [c75]Michal Kekely, Jan Korenek:
Optimizing Packet Classification on FPGA. DDECS 2023: 7-12 - [c74]Jakub Cabal, Vladislav Válek, Martin Spinler, Daniel Kondys, Jan Korenek:
400G Ethernet Packet Capture Demo Based on Network Development Kit for FPGAs. INFOCOM Workshops 2023: 1-2 - [c73]Vlastimil Kosar
, Lukas Sismis
Accelerating IDS Using TLS Pre-Filter in FPGA. ISCC 2023: 436-442 - [c72]Lukas Sismis
Analysis of TLS Prefiltering for IDS Acceleration. PAM 2023: 85-109 - 2022
- [j5]Jirí Matousek
ClassBench-ng: Benchmarking Packet Classification Algorithms in the OpenFlow Era. IEEE/ACM Trans. Netw. 30(5): 1912-1925 (2022) - [c71]Jakub Cabal, Jiri Sikora, Stepán Friedl, Martin Spinler, Jan Korenek:
FPL Demo: 400G FPGA Packet Capture Based on Network Development Kit. FPL 2022: 474 - 2021
- [c70]Roman Vrána, Jan Korenek:
Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis. DDECS 2021: 115-118 - [c69]Tomás Fukac, Jirí Matousek, Jan Korenek, Lukás Kekely:
Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks. FPT 2021: 1-9 - [c68]Tomás Fukac, Jan Korenek, Jirí Matousek:
Scalability of Hash-Based Pattern Matching for High-Speed Network Security and Monitoring. ISCC 2021: 1-6 - 2020
- [j4]Michal Kekely, Lukás Kekely
General memory efficient packet matching FPGA architecture for future high-speed networks. Microprocess. Microsystems 73: 102950 (2020) - [c67]Lukás Kekely, Jakub Cabal, Viktor Pus, Jan Korenek:
Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. DSD 2020: 49-56 - [c66]Tomás Fukac, Vlastimil Kosar
Increasing Throughput of Intrusion Detection Systems by Hash-Based Short String Pre-filter. LCN 2020: 509-514 - [c65]Jan Kucera
Enabling Event-Triggered Data Plane Monitoring. SOSR 2020: 14-26
2010 – 2019
- 2019
- [c64]Lukás Kekely
Effective FPGA Architecture for General CRC. ARCS 2019: 211-223 - [c63]Tomas Fukac, Jan Korenek:
Hash-based Pattern Matching for High Speed Networks. DDECS 2019: 1-5 - [c62]Roman Vrana
Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic. DDECS 2019: 1-6 - [c61]Milan Ceska
Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata. FCCM 2019: 109-117 - [i2]Milan Ceska, Vojtech Havlena, Lukás Holík, Jan Korenek, Ondrej Lengál, Denis Matousek, Jirí Matousek, Jakub Semric, Tomás Vojnar:
Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata. CoRR abs/1904.10786 (2019) - 2018
- [c60]Denis Matousek, Juraj Kubis, Jirí Matousek, Jan Korenek:
Regular expression matching with pipelined delayed input DFAs for high-speed networks. ANCS 2018: 104-110 - [c59]Michal Kekely, Lukas Kekely
Memory Aware Packet Matching Architecture for High-Speed Networks. DSD 2018: 1-8 - [c58]Denis Matousek, Jirí Matousek, Jan Korenek:
High-Speed Regular Expression Matching with Pipelined Memory-Based Automata. FCCM 2018: 214 - [c57]Jakub Cabal, Pavel Benácek, Lukas Kekely
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. FPGA 2018: 249-258 - [c56]Lukas Kekely
Accelerated Wire-Speed Packet Capture at 200 Gbps. FPL 2018: 455-456 - [c55]Jakub Cabal, Lukás Kekely
High-Speed Computation of CRC Codes for FPGAs. FPT 2018: 234-237 - [c54]Lukás Kekely
Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput. FPT 2018: 381-384 - [c53]Jan Kucera
General IDS Acceleration for High-Speed Networks. ICCD 2018: 366-373 - [c52]Lukas Kekely
Live demonstration of FPGA based networking accelerator for 200 Gbps data transfers. NOMS 2018: 1-3 - [i1]Jan Kucera
Seek and Push: Detecting Large Traffic Aggregates in the Dataplane. CoRR abs/1805.05993 (2018) - 2017
- [j3]Roland Dobai, Jan Korenek, Lukás Sekanina:
Evolutionary design of hash function pairs for network filters. Appl. Soft Comput. 56: 173-181 (2017) - [c51]Jirí Matousek, Gianni Antichi
ClassBench-ng: Recasting ClassBench after a Decade of Network Evolution. ANCS 2017: 204-216 - [c50]Michal Kekely, Jan Korenek:
Packet Classification with Limited Memory Resources. DSD 2017: 179-183 - [c49]Pavel Benácek, Viktor Pus, Jan Korenek, Michal Kekely:
Line rate programmable packet processing in 100Gb networks. FPL 2017: 1 - [c48]Michal Kekely, Jan Korenek:
Mapping of P4 match action tables to FPGA. FPL 2017: 1-2 - 2016
- [j2]David Grochol, Lukás Sekanina, Martin Zádník, Jan Korenek, Vlastimil Kosar
Evolutionary circuit design for fast FPGA-based classification of network application protocols. Appl. Soft Comput. 38: 933-941 (2016) - [j1]Lukas Kekely
Software Defined Monitoring of Application Protocols. IEEE Trans. Computers 65(2): 615-626 (2016) - [c47]Václav Bartos
Evaluating Reputation of Internet Entities. AIMS 2016: 132-136 - [c46]Vlastimil Kosar
Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA. DSD 2016: 591-598 - [c45]Jan Viktorin, Jan Korenek:
Packet processing on FPGA SoC with DPDK. FPL 2016: 1-2 - [c44]Denis Matousek, Jan Korenek, Viktor Pus:
High-speed regular expression matching with pipelined automata. FPT 2016: 93-100 - [c43]Roland Dobai, Jan Korenek, Lukás Sekanina:
Adaptive development of hash functions in FPGA-based network routers. SSCI 2016: 1-8 - 2015
- [c42]Vlastimil Kosar
Towards Efficient Field Programmable Pattern Matching Array. DSD 2015: 1-8 - [c41]David Grochol, Lukás Sekanina, Martin Zádník, Jan Korenek:
A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP. EvoApplications 2015: 67-78 - [c40]Viktor Pus, Petr Velan
Hardware accelerated flow measurement of 100 Gb ethernet. IM 2015: 1147-1148 - [c39]Roland Dobai, Jan Korenek:
Evolution of Non-Cryptographic Hash Function Pairs for FPGA-Based Network Applications. SSCI 2015: 1214-1219 - 2014
- [c38]Jan Viktorin, Pavol Korcek, Tomas Fukac, Jan Korenek:
Network monitoring probe based on Xilinx Zynq. ANCS 2014: 237-238 - [c37]Milan Dvorak, Jan Korenek:
Low latency book handling in FPGA for high frequency trading. DDECS 2014: 175-178 - [c36]Viktor Pus, Lukas Kekely
Design methodology of configurable high performance packet parser for FPGA. DDECS 2014: 189-194 - [c35]Lukas Kekely
Fast lookup for dynamic packet filtering in FPGA. DDECS 2014: 219-222 - [c34]Vlastimil Kosar
On NFA-split architecture optimizations. DDECS 2014: 274-277 - [c33]Lukas Kekely
Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring. FPL 2014: 1-4 - [c32]Lukas Kekely
Software Defined Monitoring of application protocols. INFOCOM 2014: 1725-1733 - [e1]Petr Hlinený, Zdenek Dvorák
Mathematical and Engineering Methods in Computer Science - 9th International Doctoral Workshop, MEMICS 2014, Telč, Czech Republic, October 17-19, 2014, Revised Selected Papers. Lecture Notes in Computer Science 8934, Springer 2014, ISBN 978-3-319-14895-3 [contents] - 2013
- [c31]Jan Viktorin, Pavol Korcek, Vlastimil Kosar, Jan Korenek:
Framework for fast prototyping of applications running on reconfigurable system on chip. DASIP 2013: 347-348 - [c30]Jan Korenek:
Hardware acceleration in computer networks. DDECS 2013: 11 - [c29]Jirí Matousek, Martin Skacan, Jan Korenek:
Towards hardware architecture for memory efficient IPv4/IPv6 Lookup in 100 Gbps networks. DDECS 2013: 108-111 - [c28]Jan Kastil
Hardware architecture for the fast pattern matching. DDECS 2013: 120-123 - [c27]Jirí Matousek, Martin Skacan, Jan Korenek:
Memory efficient IP lookup in 100 GBPS networks. FPL 2013: 1-8 - [c26]Vlastimil Kosar
NFA reduction for regular expressions matching using FPGA. FPT 2013: 338-341 - 2012
- [c25]Viktor Pus, Lukas Kekely
Low-latency modular packet header parser for FPGA. ANCS 2012: 77-78 - [c24]Jan Korenek, Pavol Korcek, Vlastimil Kosar
A new embedded platform for rapid development of network applications. ANCS 2012: 81-82 - [c23]Viktor Pus, Jan Korenek:
Reducing memory in high-speed packet classification. IWCMC 2012: 437-442 - 2011
- [c22]Viktor Pus, Jiri Tobola, Vlastimil Kosar
Netbench: Framework for Evaluation of Packet Processing Algorithms. ANCS 2011: 95-96 - [c21]Viktor Pus, Michal Kajan, Jan Korenek:
Hardware architecture for packet classification with prefix coloring. DDECS 2011: 231-236 - [c20]Jiri Tobola, Jan Korenek:
Effective hash-based IPv6 longest prefix match. DDECS 2011: 325-328 - [c19]Vlastimil Kosar
Reduction of FPGA resources for regular expression matching by relation similarity. DDECS 2011: 401-402 - 2010
- [c18]Jan Kastil
High speed pattern matching algorithm based on deterministic finite automata with faulty transition table. ANCS 2010: 7 - [c17]Michal Kajan, Jan Korenek:
Efficient packet classification algorithm based on entropy. ANCS 2010: 11 - [c16]Jan Korenek, Vlastimil Kosar
NFA split architecture for fast regular expression matching. ANCS 2010: 14 - [c15]Jan Korenek, Vlastimil Kosar
Efficient mapping of nondeterministic automata to FPGA for fast regular expression matching. DDECS 2010: 54-59 - [c14]Jan Kastil
Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashing. DDECS 2010: 149-152 - [c13]Viktor Pus, Juraj Blaho, Jan Korenek:
Memory optimizations for packet classification algorithms in FPGA. DDECS 2010: 297-300
2000 – 2009
- 2009
- [c12]Juraj Blaho, Jan Korenek, Viktor Pus:
Memory optimization for packet classification algorithms. ANCS 2009: 165-166 - [c11]Petr Kobierský, Jan Korenek, Libor Polcak:
Packet header analysis and field extraction for multigigabit networks. DDECS 2009: 96-101 - [c10]Jan Kastil
Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing. DSD 2009: 823-829 - [c9]Viktor Pus, Jan Korenek:
Fast and scalable packet classification using perfect hash functions. FPGA 2009: 229-236 - 2008
- [c8]Martin Zádník, Jan Korenek, Petr Kobierský, Ondrej Lengál
Network Probe for Flexible Flow Monitoring. DDECS 2008: 213-218 - [c7]Tamas Malek, Tomás Martínek
GICS: Generic interconnection system. FPL 2008: 263-268 - 2007
- [c6]Jan Korenek, Petr Kobierský:
Intrusion Detection System Intended for Multigigabit Networks. DDECS 2007: 361-364 - [c5]Jiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek
Online Protocol Testing for FPGA Based Fault Tolerant Systems. DSD 2007: 676-679 - [c4]Martin Kosek, Jan Korenek:
FlowContext: Flexible Platform for Multigigabit Stateful Packet Processing. FPL 2007: 804-807 - 2006
- [c3]Tomás Martínek
A Flexible Technique for the Automatic Design of Approximate String Matching Architectures. DDECS 2006: 83-84 - 2005
- [c2]Martin Zádník, Tomas Pecenka, Jan Korenek:
NetFlow Probe Intended for High-Speed Networks. FPL 2005: 695-698 - [c1]Jan Korenek, Lukás Sekanina:
Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs. ICES 2005: 46-55
Coauthor Index
aka: Lukás Kekely
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last updated on 2024-09-22 23:37 CEST by the dblp team
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