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27th PACT 2018: Limassol, Cyprus
- Skevos Evripidou, Per Stenström, Michael F. P. O'Boyle:
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, PACT 2018, Limassol, Cyprus, November 01-04, 2018. ACM 2018
Emerging applications & systems
- Vasileios Zois, Divya Gupta, Vassilis J. Tsotras
, Walid A. Najjar
Massively parallel skyline computation for processing-in-memory architectures. 1:1-1:12 - Wanling Gao, Jianfeng Zhan, Lei Wang, Chunjie Luo, Daoyi Zheng, Fei Tang, Biwei Xie, Chen Zheng, Xu Wen, Xiwen He, Hainan Ye, Rui Ren:
Data motifs: a lens towards fully understanding big data and AI workloads. 2:1-2:14 - Sanchit Misra, Tony C. Pan
Performance extraction and suitability analysis of multi- and many-core architectures for next generation sequencing secondary analysis. 3:1-3:14
Memory systems
- Biswabandan Panda, André Seznec
Synergistic cache layout for reuse and compression. 4:1-4:13 - Jinsu Park, Seongbeom Park, Myeonggyun Han, Jihoon Hyun, Woongki Baek:
Hypart: a hybrid technique for practical memory bandwidth partitioning on commodity servers. 5:1-5:14 - Jeongkyu Hong
EAR: ECC-aided refresh reduction through 2-D zero compression. 6:1-6:11
Graph processing
- Maciej Besta, Dimitri Stanojevic, Tijana Zivic, Jagpreet Singh, Maurice Hoerold, Torsten Hoefler:
Log(graph): a near-optimal high-performance graph representation. 7:1-7:13 - Pengcheng Yao
An efficient graph accelerator with parallel data conflict management. 8:1-8:12 - Zhen Peng, Alexander Powell, Bo Wu, Tekin Bicer
Graphphi: efficient parallel graph processing on emerging throughput-oriented architectures. 9:1-9:14
Compiler optimization
- Peng Jiang
Revealing parallel scans and reductions in recurrences through function reconstruction. 10:1-10:13 - Sooraj Puthoor, Mikko H. Lipasti:
Compiler assisted coalescing. 11:1-11:11 - Vasileios Porpodas, Rodrigo C. O. Rocha, Luís F. W. Góes
VW-SLP: auto-vectorization with adaptive vector width. 12:1-12:15
Parallelization management
- Adrià Armejach
Stencil codes on a vector length agnostic architecture. 13:1-13:12 - Younghyun Cho, Camilo A. Celis Guzman, Bernhard Egger
Maximizing system utilization via parallelism management for co-located parallel applications. 14:1-14:14 - Prakash Prabhu, Stephen R. Beard, Sotiris Apostolakis, Ayal Zaks, David I. August:
MemoDyn: exploiting weakly consistent data structures for dynamic parallel memoization. 15:1-15:12
Machine learning architectures
- Animesh Jain, Michael A. Laurenzano, Gilles A. Pokam, Jason Mars, Lingjia Tang:
Architectural support for convolutional neural networks on modern CPUs. 16:1-16:13 - Young H. Oh, Quan Quan, Daeyeon Kim, Seonghak Kim, Jun Heo, Sungjun Jung, Jaeyoung Jang, Jae W. Lee:
A portable, automatic data qantizer for deep neural networks. 17:1-17:14 - Franyell Silfa, Gem Dot, José-María Arnau, Antonio González:
E-PUR: an energy-efficient processing unit for recurrent neural networks. 18:1-18:12
Runtime
- Francisco Romero, Christina Delimitrou:
Mage: online and interference-aware scheduling for multi-scale heterogeneous systems. 19:1-19:13 - Bang Di, Jianhua Sun, Dong Li, Hao Chen, Zhe Quan:
GMOD: a dynamic GPU memory overflow detector. 20:1-20:13 - Younghyun Cho, Florian Negele, Seohong Park, Bernhard Egger
On-the-fly workload partitioning for integrated CPU/GPU architectures. 21:1-21:13
Storage systems
- Sukhan Lee, Kiwon Lee, Min Chul Sung, Mohammad Alian
3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions. 22:1-22:12 - Jiang Zhou, Yong Chen
Atributed consistent hashing for heterogeneous storage systems. 23:1-23:12 - Wei Zhang
DART: distributed adaptive radix tree for efficient affix-based keyword search on HPC systems. 24:1-24:12
Best paper session
- Arthur Perais
Cost effective speculation with the omnipredictor. 25:1-25:13 - Long Zheng, Xiaofei Liao, Hai Jin, Bingsheng He
Towards concurrency race debugging: an integrated approach for constraint solving and dynamic slicing. 26:1-26:13 - Arun Thangamani, V. Krishna Nandivada
Optimizing remote data transfers in X10. 27:1-27:15 - Wim Heirman, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, Ibrahim Hur:
Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors. 28:1-28:11
Programming models & compilers
- Michael LeBeane, Khaled Hamidouche, Brad Benton, Maurício Breternitz
ComP-net: command processor networking for efficient intra-kernel communications on GPUs. 29:1-29:13 - Vladimir Kiriansky, Haoran Xu, Martin C. Rinard, Saman P. Amarasinghe
Cimple: instruction and memory level parallelism: a DSL for uncovering ILP and MLP. 30:1-30:16 - Pedro Ramos, Gleison Souza Diniz Mendonca, Divino Soares, Guido Araújo, Fernando Magno Quintão Pereira:
Automatic annotation of tasks in structured code. 31:1-31:13 - Prithayan Barua, Jun Shirako, Vivek Sarkar:
Cost-driven thread coarsening for GPU kernels. 32:1-32:14
Memory and acceleration
- Sunjae Park, Christopher J. Hughes
Transactional pre-abort handlers in hardware transactional memory. 33:1-33:11 - Amir Yazdanbakhsh
In-DRAM near-data approximate acceleration for GPUs. 34:1-34:14 - Jiho Choi, Thomas Shull, Josep Torrellas:
Biased reference counting: minimizing atomic operations in garbage collection. 35:1-35:12 - Tony Nowatzki, Newsha Ardalani, Karthikeyan Sankaralingam, Jian Weng:
Hybrid optimization/heuristic instruction scheduling for programmable accelerator codesign. 36:1-36:15
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