The 10th generation 16-core sparc64™ processor for mission critical unix server

…, R Nishiyama, S Sakabayashi… - IEEE Journal of Solid …, 2013 - ieeexplore.ieee.org
A 10th generation SPARC64 processor, fabricated in enhanced 28 nm CMOS, runs at 3.0
GHz and contains 16 cores with 24 MB shared L2 cache and system/DDR3/PCIe interfaces in …
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A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution

…, Y Terao, S Honda, S Sakabayashi… - 2014 Symposium on …, 2014 - ieeexplore.ieee.org
A 36-Gbps transceiver with a continuous-time linear equalizer and a 1-tap DFE in 20-nm
CMOS is demonstrated. The transceiver uses a quarter-rate (ie, 9-GHz) differential-clock …
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An equalizer-adaptation logic for a 25-Gb/s wireline receiver in 28-nm CMOS

T Nakao, Y Hidaka, S Sakabayashi… - 2013 IEEE Asian …, 2013 - ieeexplore.ieee.org
We present an adaptation scheme for a wireline-receiver equalizer composed of a feed-forward
equalizer (FFE) and a decision-feedback equalizer (DFE), where the FFE is a cascaded …
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ミッションクリティカル UNIX サーバ向け第 10 世代 16 コア SPARC64 プロセッサ

菅竜二， 田中智浩， 杉崎剛， 西山龍一… - … 技術研究報告; 信学技 …, 2013 - ken.ieice.org
(和) 28nm CMOS プロセスを用いて 16 コア, 24MB 共有 2 次キャッシュ, システム/DDR3/PCIe
インターフェースを搭載し, 3.0 GHz で動作する, 第 10 世代の SPARC64 プロセッサ SPARC64 X を…
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