pcm-latency write-ddr latency is wrong？ #565

ZouTaooo · 2023-07-05T05:51:29Z

In Ice Lake micro architecture, the relevent event is below (come from some intel manual.):

event	evsel	umask	desc
RPQ_INSERTS.PCH0	0x10	bxxxxxxx1	Read Pending Queue Allocations
RPQ_INSERTS.PCH1	0x10	bxxxxxx1x	Read Pending Queue Allocations
RPQ_OCCUPANCY_PCH0	0x80	0x00	Read Pending Queue Occupancy
RPQ_OCCUPANCY_PCH1	0x81	0x00	Read Pending Queue Occupancy
WPQ_INSERTS.PCH0	0x20	bxxxxxxx1	Write Pending Queue Allocations
WPQ_INSERTS.PCH1	0x20	bxxxxxx1x	Write Pending Queue Allocations
WPQ_OCCUPANCY_PCH0	0x82	0x00	Write Pending Queue Occupancy
WPQ_OCCUPANCY_PCH1	0x83	0x00	Write Pending Queue Occupancy

I found the event of DRAM WPQ Occupany is incorrect. It should be 0x82. And the umask of rpq-occupancy should be zero, the umask of wpq-insert should be one.

The source code is below, in cpucounters.cpp.

Or I am wrong?
Please give a answer. Thank you!

PCM::ErrorCode PCM::programServerUncoreLatencyMetrics(bool enable_pmm)
{
    uint32 DDRConfig[4] = {0,0,0,0};

    if (enable_pmm == false)
    {   //DDR is false
        if (ICX == cpu_model || SPR == cpu_model)
	{
            DDRConfig[0] = MC_CH_PCI_PMON_CTL_EVENT(0x80) + MC_CH_PCI_PMON_CTL_UMASK(1);  // DRAM RPQ occupancy
            DDRConfig[1] = MC_CH_PCI_PMON_CTL_EVENT(0x10) + MC_CH_PCI_PMON_CTL_UMASK(1);  // DRAM RPQ Insert
            DDRConfig[2] = MC_CH_PCI_PMON_CTL_EVENT(0x81) + MC_CH_PCI_PMON_CTL_UMASK(0);  // DRAM WPQ Occupancy
            DDRConfig[3] = MC_CH_PCI_PMON_CTL_EVENT(0x20) + MC_CH_PCI_PMON_CTL_UMASK(0);  // DRAM WPQ Insert

	} else {

            DDRConfig[0] = MC_CH_PCI_PMON_CTL_EVENT(0x80) + MC_CH_PCI_PMON_CTL_UMASK(0);  // DRAM RPQ occupancy
            DDRConfig[1] = MC_CH_PCI_PMON_CTL_EVENT(0x10) + MC_CH_PCI_PMON_CTL_UMASK(0);  // DRAM RPQ Insert
            DDRConfig[2] = MC_CH_PCI_PMON_CTL_EVENT(0x81) + MC_CH_PCI_PMON_CTL_UMASK(0);  // DRAM WPQ Occupancy
            DDRConfig[3] = MC_CH_PCI_PMON_CTL_EVENT(0x20) + MC_CH_PCI_PMON_CTL_UMASK(0);  // DRAM WPQ Insert
	}
    } else {
        DDRConfig[0] = MC_CH_PCI_PMON_CTL_EVENT(0xe0) + MC_CH_PCI_PMON_CTL_UMASK(1);  // PMM RDQ occupancy
        DDRConfig[1] = MC_CH_PCI_PMON_CTL_EVENT(0xe3) + MC_CH_PCI_PMON_CTL_UMASK(0);  // PMM RDQ Insert
        DDRConfig[2] = MC_CH_PCI_PMON_CTL_EVENT(0xe4) + MC_CH_PCI_PMON_CTL_UMASK(1);  // PMM WPQ Occupancy
        DDRConfig[3] = MC_CH_PCI_PMON_CTL_EVENT(0xe7) + MC_CH_PCI_PMON_CTL_UMASK(0);  // PMM WPQ Insert
    }

    if (DDRLatencyMetricsAvailable())
    {
        for (size_t i = 0; i < (size_t)serverUncorePMUs.size(); ++i)
        {
            serverUncorePMUs[i]->programIMC(DDRConfig);
        }
    }
    return PCM::Success;
}

rdementi · 2023-07-17T11:35:16Z

thanks for reporting this. We will take a look with the developer

ZouTaooo · 2023-08-01T09:10:22Z

Thanks.
Looking forward to your reply.

sravisun · 2023-08-09T21:49:00Z

Hi @ZouTaooo,

Thank you reporting this bug.
-Currently the code only reports out DDR read latency and not write latency. Though we can make the necessary event change to update the WPQ occupancy and inserts, it will not be reported out.
-The RPQ inserts needs to be updated as pointed out above. Ran with both the scenarios (inserts with umask 0 and 1), both the scenarios reports the same number.
Though we need to update the values in code, there is no direct impact on the latency reported.

Thank you

ZouTaooo · 2023-08-10T01:34:23Z

I hava two quesitons：

No matter impact，is my idea right or wrong？Because I want to get write latency.
Why not report the write latency？I think it‘s a important metric like read latency.

intel locked and limited conversation to collaborators Oct 13, 2024

opcm converted this issue into discussion #857 Oct 13, 2024

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pcm-latency write-ddr latency is wrong？ #565

pcm-latency write-ddr latency is wrong？ #565

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pcm-latency write-ddr latency is wrong？ #565

pcm-latency write-ddr latency is wrong？ #565

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