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This system promoted a useful set of logic values that typical CMOS logic design could utilize in the vast majority of modeling situations. The 'Z' literal makes [[Three-state logic|tri-state buffer]] logic easy. The 'H' and 'L' weak drives permit [[Wired logic connection#The wired AND connection|wired-AND]] and [[Wired logic connection#The wired OR connection|wired-OR]] logic. Additionally, the 'U' state is the default value for all object declarations so that during simulations uninitialized values are easily detectable and thus easily corrected if necessary.
In [[VHDL]], the hardware designer makes the declarations visible via the following <code>library</code> and <code>use</code> statements:
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