HiSilicon

HiSilicon was Huawei's ASIC design center, which was founded in 1991.

• 2004– Shenzhen HiSilicon Semiconductor Co., Ltd. was registered and the company was formally established.
• 2016– HiSilicon's Kirin 960 chipset was rated one of the "best of Android 2016" in performance by Android Authority.^[9]
• 2019– Shanghai HiSilicon, a wholly-owned subsidiary of Huawei, was established.^[10]

 

HiSilicon develops SoCs based on the ARM architecture. Though not exclusive, these SoCs see preliminary use in handheld and tablet devices of its parent company Huawei.

The first well known product of HiSilicon is the K3V2 used in Huawei Ascend D Quad XL (U9510) smartphones^[11] and Huawei MediaPad 10 FHD7 tablets. This chipset is based on the ARM Cortex-A9 MPCore fabbed at 40 nm and uses a 16 core Vivante GC4000 GPU.^[12] The SoC supports LPDDR2-1066, but actual products are found with LPDDR-900 instead for lower power consumption.

This is a revised version of K3V2 SoC with improved support of Intel baseband. The SoC supports LPDDR2-1066, but actual products are found with LPDDR-900 instead for lower power consumption.

• supports – USB 2.0 / 13 MP / 1080p video encode

• DaVinci NPU based on Tensor Arithmetic Unit
• Kirin 820 supported 5G NSA & SA

HiSilicon Kirin 8000 is a mid-range Kirin 8 series chip not officially announced, however, it was released along with the announcement of Huawei nova 12.^[18]

• The Kirin 920 SoC also contains an image processor that supports up to 32-megapixel

• supports – SD 3.0 (UHS-I) / eMMC 4.51 / Dual-band a/b/g/n Wi-Fi / Bluetooth 4.0 Low Energy / USB 2.0 / 32 MP ISP / 1080p video encode

• supports – SD 4.1 (UHS-II) / UFS 2.0 / eMMC 5.1 / MU-MIMO 802.11ac Wi-Fi / Bluetooth 4.2 Smart / USB 3.0 / NFS / Dual ISP (42 MP) / Native 10-bit 4K video encode / i5 coprocessor / Tensilica HiFi 4 DSP

• Interconnect: ARM CCI-550, Storage: UFS 2.1, eMMC 5.1, Sensor Hub: i6

• Interconnect: ARM CCI-550, Storage: UFS 2.1, Sensor Hub: i7
• Cadence Tensilica Vision P6 DSP.^[27]
• NPU made in collaboration with Cambricon Technologies. 1.92T FP16 OPS.^[28]

Kirin 980 is HiSilicon's first SoC based on 7 nm FinFET technology.

• Interconnect: ARM Mali G76-MP10, Storage: UFS 2.1, Sensor Hub: i8
• Dual NPU made in collaboration with Cambricon Technologies.

Kirin 985 5G is the second Hisilicon's 5G SoC based on 7 nm FinFET Technology.

• Interconnect: ARM Mali-G77 MP8, Storage UFS 3.0
• Big-Tiny Da Vinci NPU: 1x Da Vinci Lite + 1x Da Vinci Tiny

Kirin 990 5G is HiSilicon's first 5G SoC based on N7 nm+ FinFET technology.^[30]

• Interconnect
  • Kirin 990 4G: ARM Mali-G76 MP16
  • Kirin 990 5G: ARM Mali-G76 MP16
  • Kirin 990E 5G: ARM Mali-G76 MP14
• Da Vinci NPU.
  • Kirin 990 4G: 1x Da Vinci Lite + 1x Da Vinci Tiny
  • Kirin 990 5G: 2x Da Vinci Lite + 1x Da Vinci Tiny
  • Kirin 990E 5G: 1x Da Vinci Lite + 1x Da Vinci Tiny
• Da Vinci Lite features 3D Cube Tensor Computing Engine (2048 FP16 MACs + 4096 INT8 MACs), Vector unit (1024bit INT8/FP16/FP32)
• Da Vinci Tiny features 3D Cube Tensor Computing Engine (256 FP16 MACs + 512 INT8 MACs), Vector unit (256bit INT8/FP16/FP32)^[31]

Kirin 9000 is HiSilicon's first SoC based on 5 nm+ FinFET (EUV) TSMC technology (N5 node) and the first 5 nm SoC to be launched on the international market.^[32] This octa-core system on a chip is based on the 9th Gen of the HiSilicon Kirin series and is equipped with 15.3 billion transistors in a 1+3+4 core configuration: 4 Arm Cortex-A77 CPU (1x 3.13 GHz and 3x 2.54 GHz), 4 Arm Cortex-A55 (4x 2.05 GHz) and a 24-core Mali-G78 GPU (22-core in the Kirin 9000E version) The Kirin 9000L uses a 1+2+3 core configuration: 3 Arm Cortex-A77 (1x 3.13 GHz and 2x 2.54 GHz), 3 Arm Cortex-A55 (3x 2.05 GHz) and a 22-core Mali-G78 GPU with Kirin Gaming+ 3.0 implementation.^[32]

The integrated quad pipeline NPU (Dual Big Core + 1 Tiny Core configuration) is equipped with the Kirin ISP 6.0 to support advanced computational photography. The Huawei Da Vinci Architecture 2.0 for AI supports 2x Ascend Lite + 1x Ascend Tiny (only 1 Lite in 9000E/L). The system cache is 8 MB and the SoC works with the new LPDDR5/4X memories (made by Samsung in the Huawei Mate 40 series). Due to the integrated 3rd generation 5G proprietary modem "Balong 5000", Kirin 9000 supports 2G, 3G, 4G and 5G SA & NSA Sub-6 GHz connectivity.^[32] The SoC's TDP is 6W.

The 2021 4G version of the Kirin 9000 has the Balong modem limited via software to comply with the ban imposed on Huawei by the US government for non-chinese 5G technologies. The Kirin 9006C is a rebranded variant of the Kirin 9000E for the Huawei Qingyun L420 and L540 laptops.^[33][34]

• GPU
  • Kirin 9000L: ARM Mali-G78 MP22
  • Kirin 9000E: ARM Mali-G78 MP22
  • Kirin 9000: ARM Mali-G78 MP24
• Da Vinci NPU architecture 2.0
  • Kirin 9000L: 1x Big Core + 1x Tiny Core
  • Kirin 9000E: 1x Big Core + 1x Tiny Core
  • Kirin 9000: 2x Big Cores + 1x Tiny Core

The Kirin 9000S, Kirin 9000S1, and Kirin 9010 of the Kirin 9000 Hi36A0 family are the first HiSilicon-developed SoCs manufactured in high volumes in mainland China by SMIC. The SoC had its debut with the Huawei Mate 60 in late 2023 with the Kirin 9000S alongside overclocked enhancements of the Kirin 9000S1 and Kirin 9010 with the Huawei Pura 70 series in early 2024.^[35] According to Tom's Hardware, the Taishan V120 core, developed by HiSilicon, was roughly on par with AMD's Zen 3 cores from late 2020.^[36] Four of these cores were used in the 9000 series alongside four efficiency-focused Arm Cortex-A510 cores.^[37] The SoCs are based on SMIC's 7nm technology node, referred to as "N+2". It also includes 1 Da Vinci "big" NPU core and 1 Da Vinci "small" NPU core. Kirin 9000W, a Wi-Fi only SoC for the Huawei MatePad Pro 13.2 Wi-Fi only model, debuted in global markets in Q1 2024. The Kirin 9010 and Kirin 9000S1 debuted in Q2 2024, using a modified 2+6+4 core configuration with a new large Taishan core with the same configurations of medium and small cores from the Kirin 9000S with faster enhancements over the Kirin 9000S.^[38]

HiSilicon develops smartphone modems which are primarily used in its parent company Huawei's handheld and tablet devices.

The Balong 700 supports LTE TDD/FDD.^[41] Its specs:

• 3GPP R8 protocol
• LTE TDD and FDD
• 4x2/2x2 SU-MIMO

At MWC 2012, HiSilicon released the Balong 710.^[42] It is a multi-mode chipset supporting 3GPP Release 9 and LTE Category 4 at GTI (Global TD-LTE Initiative). The Balong 710 was designed to be used with the K3V2 SoC. Its specs:

• LTE FDD mode : 150 Mbit/s downlink and 50 Mbit/s uplink.
• TD-LTE mode: up to 112 Mbit/s downlink and up to 30 Mbit/s uplink.
• WCDMA Dual Carrier with MIMO: 84 Mbit/s downlink and 23 Mbit/s uplink.

The Balong 720 supports LTE Cat6 with 300 Mbit/s peak download rate.^[41] Its specs:

• TSMC 28 nm HPM process
• TD-LTE Cat.6 standard
• Dual-carrier aggregation for the 40 MHz bandwidth
• 5-mode LTE Cat6 Modem

The Balong 750 supports LTE Cat 12/13, and it is first to support 4CC CA and 3.5 GHz.^[41] Its specs:

• LTE Cat.12 and Cat.13 UL network standards
• 2CC (dual-carrier) data aggregation
• 4x4 multiple-input multiple-output (MIMO)
• TSMC 16 nm FinFET+ process

The Balong 765 supports 8×8 MIMO technology, LTE Cat.19 with downlink data-rate up to 1.6 Gbit/s in FDD network and up to 1.16 Gbit/s in the TD-LTE network.^[43] Its specs:

• 3GPP Rel.14
• LTE Cat.19 Peak data rate up to 1.6 Gbit/s
• 4CC CA + 4×4 MIMO/2CC CA + 8×8 MIMO
• DL 256QAM
• C-V2X

The Balong 5G01 supports the 3GPP standard for 5G with downlink speeds of up to 2.3 Gbit/s. It supports 5G across all frequency bands including sub-6 GHz and millimeter wave (mmWave).^[41] Its specs:

• 3GPP Release 15
• Peak data rate up to 2.3 Gbit/s
• Sub-6 GHz and mmWave
• NSA/SA
• DL 256QAM

The Balong 5000 is the world's first 7 nm TSMC 5G multi-mode chipset (launched in Q1 2019), the world's first SA/NSA implementation, and the first smartphone chipset to support the full NR TDD/FDD spectrum.^[44] The modem has an advanced 2G, 3G, 4G, and 5G connectivity.^[45] Its specs:

• 2G/3G/4G/5G Multi Mode
• Fully compliant with 3GPP Release 15
• Sub-6 GHz: 100 MHz x 2CC CA
• Sub-6 GHz: Downlink up to 4.6 Gbit/s, Uplink up to 2.5 Gbit/s
• mmWave: Downlink up to 6.5 Gbit/s, Uplink up to 3.5 Gbit/s
• NR+LTE: Downlink up to 7.5 Gbit/s
• FDD & TDD Spectrum Access
• SA & NSA Fusion Network Architecture
• Supports 3GPP R14 V2X
• 3 GB LPDDR4X RAM^[46]

HiSilicon develops SoCs for wearables such as wireless earbuds, wireless headphones, neckband earbuds, smart speakers, smart eyewear, and smartwatches.^[47]

The Kirin A1 (Hi1132) was announced on 6 September 2019.^[47] It features:

• BT/BLE dual-mode Bluetooth 5.1^[48]
• Isochronous Dual Channel transmission technology
• 356 MHz audio processor
• Cortex-M7 microprocessor

The Kirin A2 was announced on September 25, 2023.^[49] It features:

• Faster Transmission
• Stable signal with Polar code technology
• Increase of 50% in computing power performance
• Audio Vivid

HiSilicon develops server processor SoCs based on the ARM architecture.

The Hi1610 is HiSilicon's first generation server processor announced in 2015. It features:

• 16x ARM Cortex-A57 at up to 2.1 GHz^[50]
• 48 KB L1-I, 32 KB L1-D, 1 MB L2/4 cores and 16 MB CCN L3
• TSMC 16 nm
• 2x DDR4-1866
• 16 PCIe 3.0

The Hi1612 is HiSilicon's second generation server processor launched in 2016. It is the first chiplet-based Kunpeng with two computing dies. It features:

• 32x ARM Cortex-A57 at up to 2.1 GHz^[50]
• 48 KB L1-I, 32 KB L1-D, 1 MB L2/4 cores and 32 MB CCN L3
• TSMC 16 nm
• 4x DDR4-2133
• 16 PCIe 3.0

The Kunpeng 916 (formerly known as Hi1616) is HiSilicon's third generation server processor launched in 2017. The Kunpeng 916 is used in Huawei's TaiShan 2280 Balanced Server, TaiShan 5280 Storage Server, TaiShan XR320 High-Density Server Node and TaiShan X6000 High-Density Server.^{[51][52][53][54]} It features:

• 32x ARM Cortex-A72 at up to 2.4 GHz^[50]
• 48 KB L1-I, 32 KB L1-D, 1 MB L2/4 cores and 32 MB CCN L3
• TSMC 16 nm
• 4x DDR4-2400
• 2-way Symmetric multiprocessing (SMP), Each socket has 2x ports with 96 Gbit/s per port (total of 192 Gbit/s per each socket interconnects)
• 46 PCIe 3.0 and 8x 10 Gigabit Ethernet
• 85 W

The Kunpeng 920 (formerly known as Hi1620) is HiSilicon's fourth generation server processor announced in 2018, and launched in 2019. Huawei claims the Kunpeng 920 CPU scores more than an estimated 930 on SPECint_rate_base2006.^[55] The Kunpeng 920 is used in Huawei's TaiShan 2280 V2 Balanced Server, TaiShan 5280 V2 Storage Server, and TaiShan XA320 V2 High-Density Server Node.^[56][57][58] It features:

• 32 to 64x custom TaiShan V110 cores at up to 2.6 GHz.^[59]
• The TaiShan V110 core is a 4-way superscalar, out-of-order microarchitecture that implements the ARMv8.2-A ISA. Huawei reports the core supports almost all the ARMv8.4-A ISA features with a few exceptions, including the dot product and FP16 FML extensions.^[59]
• The TaiShan V110 cores are likely a new core not based on ARM designs^{[60][original research?]}
• 3x Simple ALUs, 1x Complex MDU, 2x BRUs (sharing ports with ALU2/3), 2x FSUs (ASIMD FPU), 2x LSUs^[60]
• 64 KB L1-I, 64 KB L1-D, 512 KB Private L2 and 1 MB L3/core Shared.
• TSMC 7 nm HPC
• 8x DDR4-3200
• 2-way and 4-way symmetric multiprocessing (SMP). Each socket has 3x Hydra ports with 240 Gbit/s per port (total of 720 Gbit/s per each socket interconnects)
• 40 PCIe 4.0 with CCIX support, 4x USB 3.0, 2x SATA 3.0, 8x SAS 3.0 and 2x 100 gigabit ethernet
• 100 to 200 W
• Compression engine (GZIP, LZS, LZ4) capable of up to 40 Git/s compress and 100 Gbit/s decompress
• Crypto offload engine (for AES, DES, 3DES, SHA1/2, etc..) capable of throughputs up to 100 Gbit/s

The Kunpeng 930 (formerly known as Hi1630) is HiSilicon's fifth-generation server processor announced in 2019 and scheduled for launch in 2021. It features:

• 80 custom TaishanV120 cores at 3 GHz frequency, with support for simultaneous multithreading (SMT) and ARM's Scalable Vector Extension (SVE).^[59]
• 64 KB L1-I, 64 KB L1-D, 512 KB Private L2 and 1 MB L3/core Shared
• TSMC 5 nm
• 8x DDR5

The Kunpeng 950 is HiSilicon's sixth-generation server processor announced in 2019 and scheduled for launch in 2023.

HiSilicon also develops AI Acceleration chips.

Each Da Vinci Max AI Core features a 3D Cube Tensor Computing Engine (4096 FP16 MACs + 8192 INT8 MACs), a vector unit (2048bit INT8/FP16/FP32), and a scalar unit. It includes a new AI framework called "MindSpore", a platform-as-a-service product called ModelArts, and a lower-level library called Compute Architecture for Neural Networks (CANN).^[31]

The Ascend 310 is an AI inference SoC, it was codenamed Ascend-Mini. The Ascend 310 is capable of 16 TOPS@INT8 and 8 TOPS@FP16.^[61] The Ascend 310 features:

• 2x Da Vinci Max AI cores^[31]
• 8x ARM Cortex-A55 CPU cores
• 8 MB on-chip buffer
• 16 channel video decode – H.264/H.265
• 1 channel video encode – H.264/H.265
• TSMC 12 nm FFC process
• 8W TDP

The Ascend 910 is an AI training SoC, it was codenamed Ascend-Max. which delivers 256 TFLOPS@FP16 and 512 TOPS@INT8. The Ascend 910 features:

• 32x Da Vinci Max AI cores arranged in 4 clusters^[31]
• 1024-bit NoC Mesh @ 2 GHz, with 128 GB/s bandwidth Read/Write per core
• 3x 240 Gbit/s HCCS ports for Numa connections
• 2x 100 Gbit/s RoCE interfaces for networking
• 4x HBM2E, 1.2 TB/s bandwidth
• 3D-SRAM stacked below AI SoC die
• 1228 mm² Total die size (456 mm² Virtuvian AI SoC, 168 mm² Nimbus V3 IO Die, 4x96 mm² HBM2E, 2x110 mm² Dummy Die)
• 32 MB on-chip buffer
• 128 channel video decode – H.264/H.265
• TSMC 7 nm EUV (N7+) process
• 350 W

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• Semiconductor industry in China

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