User:RastaKins

RastaKins is an electronic and software engineer.

In 1976, Rastakins' first computer job was at Industrial Micro Systems (now Cubix) assembling 8080-based XYZ controllers for chip wire bonding machines. This company quickly pivoted to the lucrative S-100 market. During a downturn, Rastakins walked across the parking lot to one of the first computer stores in the world, Computer Mart of Orange. There Rastakins got a job as a repair technician. Rastakins' supervisor was George Tate...the Tate of the future Ashton-Tate! As a sideline, Rastakins assembled, on contract, twenty-two IMSAI 8080 computers and a few Sol-20s and BYT-8s. RastaKins also designed a 16K S-100 memory board, a dot-matrix printer controller, and time of day clock board for the IMSAI.

In 1979 RastaKins then went to work for Western Digital designing their very first hard disk controller, the WD1000. This design used five gate arrays and the Signetics 8X300 microprocessor. The WD1000 controlled early fixed discs such as the Seagate ST-506. The design was quickly followed with the WD1001 ECC disk controller based on new gate arrays and the Signetics 8X305. A number of designs followed based on Western Digital's WD1010 single chip hard disc controller, including WD's first SCSI and first 1:1 interleave controller, the WD1003-SCS. RastaKins's work with error correction codes led to the architecting of the stillborn Western Digital programmable polynomial generator. RastaKins wrote the microcode for WD's WD2412 time-of-day clock chip which first saw use in the Pascal MicroEngine. The WD2412 was based on the WD4200, a COP420 copy. RastaKins started experimenting with cross-object assemblers at WD, building an assembler that would take 8080 source code and generate PDP-11 object code. RastaKins contributed to the detailed digital design and software for the hard disk controller which was shipped with all IBM ATs.^{[note 1]}

Rastakins designed or contributed to the integration of hard drive controller products for The TRS-80, IBM Instruments System 9000, Kaypro 10, Fortune Systems' 32:16^{[note 2]} and the Olivetti M20.^{[note 3]}

In 1985 RastaKins went to work at ProVUE Development, creating an improved PDP-11 (actually WD16) to Motorola 68000 cross-object assembler. The resulting object code executed 32-bit clean even though it was written in 16-bit PDP-11. That was followed by a PDP-11 to Intel 8086 cross-object assembler that implemented a 20-bit virtual machine, allowing 20-bit linear addressing on the 8086.^{[note 4]} RastaKins worked on ProVUE's SuperVUE and Panorama products.

RastaKins then worked for L'Garde, designing a number of spacecraft systems. Rastakins designed the light panels, squib fire box, IRIG telemetry interface, and software for the Inflatable Antenna Experiment which was the primary payload on Space Shuttle mission STS-77. RastaKins designed the deployment electronics for a preliminary version of AFRL's ISAT. The deployment system used a networked array of 26 rad-hard 80196 microcontrollers. RastaKins designed the electronics to be infinitely-extensible so any size truss could be built using identical building blocks. RastaKins also architected the pneumatic deployment system to mimic the electronic's infinitely-extensible characteristics. RastaKins created the original electronics design for the Sunjammer solar sail. There are 15 L’Garde-supplied microcontrollers in this design. Other projects include electronics and software systems for OCSE (2000), MTS (2006), DSX (2007), COD (2008), AO (2008), LEVR (2009), Red Tigress (2009), SCD (2010), and LTD (2011).

Rastakins created the WD16 and COP400 Wikipedia pages. Why? Rastakins has extensively programmed and admired both. The WD16 has the most elaborate instruction set of all the early 16-bit microprocessors.^{[note 5]} The COP400 has an ingenious and terse instruction set that conserves bytes. The tiny 1K ROM in the COP400-based WD2412 time-of-day clock chip has almost 900 lines of code crammed into it!

Notes

^ I helped integrate this controller at Boca Raton. The IBM guys were hiding the AT motherboard inside a pizza box. Literally a pizza box from a local pizza place. The motherboard crashed every 10 minutes or so. Each time the IBM guys would shut it off and let it cool for a few minutes. After a bunch of crashes, I told the IBM guys that I already knew that there's a 80286 on this motherboard because of its timing. The IBM guys then cut holes in the pizza box exposing the processor and another chip.
^ Since the Fortune 32:16 was all about performance, the disk controller needed to implement DMA. DMA controllers of the era typically handled only 8 bit data and 16 bit addressing. The 32:16 bus had 16 bit data and 24 bit addressing. I came up with a DMA solution that required no LSI devices nor counters. I had the 8X305 run the 24 bit counters and 8-to-16 bit bus conversion in software. The 8X300 would send addresses and data to simple, cheap octal latches. The Fortune engineers did not like this software solution because they perceived it as slow. Yet, in their own DMA specification, they required devices to not hog bus bandwidth. I demonstrated that the 8X305 software solution met both Fortune’s performance and non-bus hogging goals. The software loop required to update 16 bits of data, update the least significant byte of the address, maintain a word counter, initiate the DMA state machine, and wait for completion was only 8 8X305 instructions or 2 microseconds (us). The required 256 16-bit word DMA transfer could happen in just 512 uS. The sector time of the disk drive was about 1000 us. So my software DMA could deliver data to/from memory at full disc speed. (DMA transfers that crossed 8 bit and 16 bit address boundaries took 2.75 us and 3.25 us, respectively.)
^ But not the Osborne Executive! Western Digital would often integrate disk controllers into customer computers for free, amortizing the costs across a production run. Lee Felsenstein wanted WD to design a controller for an upcoming Osborne computer. WD's reference designs read disk data from the WD1010 hard disk controller chip into a 512 byte sector buffer. The host then transfers the block to local RAM using DMA or perhaps the Z80 INIR instruction. Felsenstein insisted that we do not use a sector buffer but instead DMA directly from the WD1010 into some unused video RAM. This made no sense as the tiny RAM chips we used for sector buffers were very cheap and Osborne video RAM would create variable latencies which would complicate the design. Felsenstein might have been fighting for this because the Osborne's I/O was curiously memory mapped which would make the Z80 INIR (block input) instruction unusable. If the sector buffer was in video RAM, he could use the Z80 LDIR (block move) instruction. I recommended to management that we should reject the Osborne project and Osborne soon went bankrupt.
^ This was used to port SuperVUE to the IBM PC. Code was in a 64K code segment. Named variables were in a fixed data segment. PDP-11 registers were implemented as an array of 16 bit segment:offsets and were stored on the stack off of BP. Data pointed to with PDP-11 registers could be anywhere in a 500 kilobyte memory space with data segments calculated for each access.
^ The WD16 expanded on the PDP-11 instruction set in many ways. For example, the PDP-11 JMP instruction can use any addressing mode. The WD16 improves upon the PDP-11 JMP by generalizing it as a LEA (load effective address) instruction which the PDP-11 lacks. On the WD16, JMP is simply encoded as a LEA PC,dest.

[1] I helped integrate this controller at Boca Raton. The IBM guys were hiding the AT motherboard inside a pizza box. Literally a pizza box from a local pizza place. The motherboard crashed every 10 minutes or so. Each time the IBM guys would shut it off and let it cool for a few minutes. After a bunch of crashes, I told the IBM guys that I already knew that there's a 80286 on this motherboard because of its timing. The IBM guys then cut holes in the pizza box exposing the processor and another chip.

[2] Since the Fortune 32:16 was all about performance, the disk controller needed to implement DMA. DMA controllers of the era typically handled only 8 bit data and 16 bit addressing. The 32:16 bus had 16 bit data and 24 bit addressing. I came up with a DMA solution that required no LSI devices nor counters. I had the 8X305 run the 24 bit counters and 8-to-16 bit bus conversion in software. The 8X300 would send addresses and data to simple, cheap octal latches. The Fortune engineers did not like this software solution because they perceived it as slow. Yet, in their own DMA specification, they required devices to not hog bus bandwidth. I demonstrated that the 8X305 software solution met both Fortune’s performance and non-bus hogging goals. The software loop required to update 16 bits of data, update the least significant byte of the address, maintain a word counter, initiate the DMA state machine, and wait for completion was only 8 8X305 instructions or 2 microseconds (us). The required 256 16-bit word DMA transfer could happen in just 512 uS. The sector time of the disk drive was about 1000 us. So my software DMA could deliver data to/from memory at full disc speed. (DMA transfers that crossed 8 bit and 16 bit address boundaries took 2.75 us and 3.25 us, respectively.)

[3] But not the Osborne Executive! Western Digital would often integrate disk controllers into customer computers for free, amortizing the costs across a production run. Lee Felsenstein wanted WD to design a controller for an upcoming Osborne computer. WD's reference designs read disk data from the WD1010 hard disk controller chip into a 512 byte sector buffer. The host then transfers the block to local RAM using DMA or perhaps the Z80 INIR instruction. Felsenstein insisted that we do not use a sector buffer but instead DMA directly from the WD1010 into some unused video RAM. This made no sense as the tiny RAM chips we used for sector buffers were very cheap and Osborne video RAM would create variable latencies which would complicate the design. Felsenstein might have been fighting for this because the Osborne's I/O was curiously memory mapped which would make the Z80 INIR (block input) instruction unusable. If the sector buffer was in video RAM, he could use the Z80 LDIR (block move) instruction. I recommended to management that we should reject the Osborne project and Osborne soon went bankrupt.

[4] This was used to port SuperVUE to the IBM PC. Code was in a 64K code segment. Named variables were in a fixed data segment. PDP-11 registers were implemented as an array of 16 bit segment:offsets and were stored on the stack off of BP. Data pointed to with PDP-11 registers could be anywhere in a 500 kilobyte memory space with data segments calculated for each access.

[5] The WD16 expanded on the PDP-11 instruction set in many ways. For example, the PDP-11 JMP instruction can use any addressing mode. The WD16 improves upon the PDP-11 JMP by generalizing it as a LEA (load effective address) instruction which the PDP-11 lacks. On the WD16, JMP is simply encoded as a LEA PC,dest.

[note 1]

[note 2]

[note 3]

[note 4]

[note 5]