Zero ASIC

Zero ASIC Corporation, formerly Adapteva, Inc., is a fabless semiconductor company focusing on low power many core microprocessor design. The company was the second company to announce a design with 1,000 specialized processing cores on a single integrated circuit.^[1][2]

Adapteva was founded in 2008 with the goal of bringing a ten times advancement in floating-point performance per watt for the mobile device market. Products are based on its Epiphany multi-core multiple instruction, multiple data (MIMD) architecture and its Parallella Kickstarter project promoting "a supercomputer for everyone" in September 2012. The company name is a combination of "adapt" and the Hebrew word "Teva" meaning nature.

Adapteva was founded in March 2008, by Andreas Olofsson. The company was founded with the goal of bringing a 10× advancement in floating-point processing energy efficiency for the mobile device market. In May 2009, Olofsson had a prototype of a new type of massively parallel multi-core computer architecture. The initial prototype was implemented in 65 nm and had 16 independent microprocessor cores. The initial prototypes enabled Adapteva to secure US$1.5 million in series-A funding from BittWare, a company from Concord, New Hampshire, in October 2009.^[3]

Adapteva's first commercial chip product started sampling to customers in early May 2011 and they soon thereafter announced the capability to put up to 4,096 cores on a single chip.

The Epiphany III, was announced in October 2011 using 28 nm and 65 nm manufacturing processes.

Adapteva's main product family is the Epiphany scalable multi-core MIMD architecture. The Epiphany architecture could accommodate chips with up to 4,096 RISC out-of-order microprocessors, all sharing a single 32-bit flat memory space. Each RISC processor in the Epiphany architecture is superscalar with 64× 32-bit unified register file (integer or single-precision) microprocessor operating up to 1 GHz and capable of 2 GFLOPS (single-precision). Epiphany's RISC processors use a custom instruction set architecture (ISA) optimised for single-precision floating-point,^[4] but are programmable in high level ANSI C using a standard GNU-GCC tool chain. Each RISC processor (in current implementations; not fixed in the architecture) has 32 KB of local memory. Code (possibly duplicated in each core) and stack space should be in that local memory; in addition (most) temporary data should fit there for full speed. Data can also be used from other processor cores local memory at a speed penalty, or off-chip RAM with much larger speed penalty.

The memory architecture does not employ explicit hierarchy of hardware caches, similar to the Sony/Toshiba/IBM Cell processor, but with the additional benefit of off-chip and inter-core loads and stores being supported (which simplifies porting software to the architecture). It is a hardware implementation of partitioned global address space.^{[citation needed]}

This eliminated the need for complex cache coherency hardware, which places a practical limit on the number of cores in a traditional multicore system. The design allows the programmer to leverage greater foreknowledge of independent data access patterns to avoid the runtime cost of figuring this out. All processor nodes are connected through a network on chip, allowing efficient message passing.^[5]

The architecture is designed to scale almost indefinitely, with 4 e-links allowing multiple chips to be combined in a grid topology, allowing for systems with thousands of cores.

On August 19, 2012, Adapteva posted some specifications and information about Epiphany multi-core coprocessors.^[6]

In September 2012, a 16-core version, the Epiphany-III (E16G301), was produced using 65 nm^[9] (11.5 mm², 500 MHz chip^[10]) and engineering samples of 64-core Epiphany-IV (E64G401) were produced using 28 nm GlobalFoundries process (800 MHz).^[11]

The primary markets for the Epiphany multi-core architecture include:

• Smartphone applications such as real-time facial recognition, speech recognition, translation, and augmented reality.
• Next generation supercomputers requiring drastically better energy efficiency to allow systems to scale to exaflop computing levels.
• Floating-point acceleration in embedded systems based on field-programmable gate array architectures.

In September 2012, Adapteva started project Parallella on Kickstarter, which was marketed as "A Supercomputer for everyone." Architecture reference manuals for the platform were published as part of the campaign to attract attention to the project.^[12] The US$750,000 funding goal was reached in a month, with a minimum contribution of US$99 entitling backers to obtain one device; although the initial deadline was set for May 2013, the first single-board computers with 16-core Epiphany chip were finally shipped in December 2013.^[13]

Size of board is planned to be 86 mm × 53 mm (3.4 in × 2.1 in).^[14][15][16]

The Kickstarter campaign raised US$898,921.^[17][18] Raising US$3 million goal was unsuccessful, so no 64-core version of Parallella will be mass-produced.^[19] Kickstarter users having donated more than US$750 will get "parallella-64" variant with 64-core coprocessor (made from initial prototype manufacturing with 50 chips yield per wafer).^[20]

By 2016, the firm had taped out a 1024-core 64-bit variant of their Epiphany architecture that featured: larger local stores (64 KB), 64-bit addressing, double-precision floating-point arithmetic or SIMD single-precision, and 64-bit integer instructions, implemented in the 16 nm process node.^[21] This design included instruction set enhancements aimed at deep-learning and cryptography applications. In July 2017, Adapteva's founder became a DARPA MTO program manager^[22] and announced that the Epiphany V was "unlikely" to become available as a commercial product.^[23]

The 16-core Parallella achieves roughly 5.0 GFLOPS/W, and the 64-core Epiphany-IV made with 28 nm estimated as 50 GFLOPS/W (single-precision),^[24] and 32-board system based on them achieves 15 GFLOPS/W.^[25] For comparison, top GPUs from AMD and Nvidia reached 10 GFLOPS/W for single-precision in 2009–2011 timeframe.^[26]

• Asynchronous array of simple processors
• SW26010 – a Chinese design featuring a similar architecture used in the Sunway TaihuLight supercomputer
• Vision Processing Unit – a class of processor with significant overlapping features

• Linley Gwennap, Adapteva: More Flops, Less Watts. Epiphany Offers Floating-Point Accelerator for Mobile Processors. // Microprocessor Report, June 2011

• Official website
• Parallella specifications