• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 50 matches

• 1992
• 
  Brian A. A. Antao, Arthur J. Brodersen:
  Techniques for Synthesis of Analog Integrated Circuits. IEEE Des. Test Comput. 9(1): 8-18 (1992)
• 
  Dominique Borrione, Robert Piloty, Dwight D. Hill, Karl J. Lieberherr, Philip Moorby:
  Three Decades of HDLs: Part II, Conlan Through Verilog. IEEE Des. Test Comput. 9(3): 54-63 (1992)
• 
  Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem:
  Formal Verification of VHDL Descriptions in the Prevail Environment. IEEE Des. Test Comput. 9(2): 42-56 (1992)
• 
  David E. van den Bout, Joseph N. Morris, Douglas Thomae, Scott Labrozzi, Scot Wingo, Peter Hallman:
  AnyBoard: An FPGA-Based, Reconfigurable System. IEEE Des. Test Comput. 9(3): 21-30 (1992)
• 
  Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar:
  DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Des. Test Comput. 9(3): 7-20 (1992)
• 
  Yaohan Chu, Donald L. Dietmeyer, James R. Duley, Fredrick J. Hill, Mario Barbacci, Charles W. Rose, Greg M. Ordy, Bill Johnson, Martin Roberts:
  Three Decades of HDLs: Part I, CDL Through TI-HDL. IEEE Des. Test Comput. 9(2): 69-81 (1992)
• 
  Bulent I. Dervisoglu:
  Boundary-Scan Update: IEEE P1149.2 Description and Status Report. IEEE Des. Test Comput. 9(3): 79-81 (1992)
• 
  Allen Dewey:
  Guest Editor's Introduction: VHDL and Next-Generation Design Automation. IEEE Des. Test Comput. 9(2): 6-7 (1992)
• 
  Allen Dewey, Aart J. de Geus:
  VHDL: Toward a Unified View of Design. IEEE Des. Test Comput. 9(2): 8-17 (1992)
• 
  Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
  Delay-Fault Diagnosis by Critical-Path Tracing. IEEE Des. Test Comput. 9(4): 27-32 (1992)
• 
  Zafar Hasan, David Harrison, Maciej J. Ciesielski:
  A Fast Partitioning Method for PLA-Based FPGAs. IEEE Des. Test Comput. 9(4): 34-39 (1992)
• 
  Steven H. Kelem, Jorge P. Seidel:
  Shortening the Design Cycle for Programmable Logic. IEEE Des. Test Comput. 9(4): 40-50 (1992)
• 
  Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh, Raja Venkateswaran:
  A Behavioral Fault Simulator for Ideal. IEEE Des. Test Comput. 9(4): 14-21 (1992)
• 
  Antonio Lioy:
  Advanced Fault Collapsing (Logic Circuits Testing). IEEE Des. Test Comput. 9(1): 64-71 (1992)
• 
  Yashwant K. Malaiya:
  Guest Editor's Introduction: VLSI Design 92. IEEE Des. Test Comput. 9(4): 4-5 (1992)
• 
  David Marple:
  An MPGA-Like FPGA. IEEE Des. Test Comput. 9(4): 51-60 (1992)
• 
  Colin M. Maunder:
  A D&T Special Report-Boundary Scan: An End-of-Term Report-IEEE Std 1149.1 Survey Results. IEEE Des. Test Comput. 9(2): 82-85 (1992)
• 
  Pat McHugh:
  IEEE P1149.5 Module Test and Maintenance Bus. IEEE Des. Test Comput. 9(4): 62-65 (1992)
• 
  Don L. Millard, Karl R. Umstadter, Robert C. Block:
  Noncontact Testing of Circuits Via a Laser-Induced Plasma Electrical Pathway. IEEE Des. Test Comput. 9(1): 55-63 (1992)
• 
  Vijay Nagasamy, Neerav Berry, Carlos Dangelo:
  Specification, Planning, and Synthesis in a VHDL Design Environment. IEEE Des. Test Comput. 9(2): 58-68 (1992)
• 
  Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
  System Specification with the SpecCharts Language. IEEE Des. Test Comput. 9(4): 6-13 (1992)
• 
  Ashish Pancholy, Janusz Rajski, Larry J. McNaughton:
  Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits. IEEE Des. Test Comput. 9(1): 72-83 (1992)
• 
  Vijay Pitchumani, Pankaj Mayor, Nimish Radia:
  A VHDL Fault Diagnosis Tool Using Functional Fault Models. IEEE Des. Test Comput. 9(2): 33-41 (1992)
• 
  Jayanta Roy, Nand Kumar, Rajiv Dutta, Ranga Vemuri:
  DSS: A Distributed High-Level Synthesis System. IEEE Des. Test Comput. 9(2): 18-32 (1992)
• 
  Kewal K. Saluja, Chin-Foo See:
  An Efficient Signature Computation Method. IEEE Des. Test Comput. 9(4): 22-26 (1992)
• 
  John W. Sheppard, William R. Simpson:
  Applying Testability Analysis for Integrated Diagnostics. IEEE Des. Test Comput. 9(3): 65-78 (1992)
• 
  William R. Simpson, John W. Sheppard:
  System Testability Assessment for Integrated Diagnostics. IEEE Des. Test Comput. 9(1): 40-54 (1992)
• 
  Mustapha Slamani, Bozena Kaminska:
  Analog Circuit Fault Diagnosis Based on Sensitivity Computation and Functional Testing. IEEE Des. Test Comput. 9(1): 30-39 (1992)
• 
  Mani Soma:
  Guest Editor's Introduction: Mixing Analog and Digital Systems. IEEE Des. Test Comput. 9(1): 6-7 (1992)
• 
  Mani B. Srivastava, Robert W. Brodersen:
  Using VHDL for High-Level, Mixed-Mode System Simulation. IEEE Des. Test Comput. 9(3): 31-40 (1992)

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