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"ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient ..."

Dhruv Gajaria, Tosiron Adegbija (2024)

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DOI: 10.48550/ARXIV.2407.19612

access: open

type: Informal or Other Publication

metadata version: 2024-08-21

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  dblp key:
  - journals/corr/abs-2407-19612
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  - https://dblp.org/rec/journals/corr/abs-2407-19612
Dhruv Gajaria, Tosiron Adegbija:
ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors. CoRR abs/2407.19612 (2024)

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