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"A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs."

Pascal Giard et al. (2015)

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DOI: 10.1109/SIPS.2015.7345007

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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  dblp key:
  - conf/sips/GiardSTG15
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  - https://dblp.org/rec/conf/sips/GiardSTG15
Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross:
A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs. SiPS 2015: 1-6

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