default search action

combined dblp search
author search
venue search
publication search

ask others

"Gated Vernier Delay Line Time Integrator for Time-Mode Signal Processing."

Parth Parekh, Fei Yuan, Yushi Zhou (2021)

> Home

Details and statistics

DOI: 10.1109/MWSCAS47672.2021.9531875

access: closed

type: Conference or Workshop Paper

metadata version: 2021-09-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/mwscas/ParekhYZ21
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/mwscas/ParekhYZ21
Parth Parekh, Fei Yuan, Yushi Zhou:
Gated Vernier Delay Line Time Integrator for Time-Mode Signal Processing. MWSCAS 2021: 1082-1085

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.