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"A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study."

Steve Haynal et al. (2008)

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DOI: 10.1109/MEMCOD.2008.4547693

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/memocode/HaynalKKSW08
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  persistent URL:
  - https://dblp.org/rec/conf/memocode/HaynalKKSW08
Steve Haynal, Timothy Kam, Michael Kishinevsky, Emily Shriver, Xinning Wang:
A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study. MEMOCODE 2008: 79-88

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