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"Via-Aware Global Routing for Good VLSI Manufacturability and High Yield."

Yang Yang et al. (2005)

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DOI: 10.1109/ASAP.2005.67

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - conf/asap/YangJHHZHY05
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  persistent URL:
  - https://dblp.org/rec/conf/asap/YangJHHZHY05
Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan:
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. ASAP 2005: 198-203

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