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"Low-Power Way-Predicting Cache Using Valid-Bit Pre-Decision for Parallel ..."

Hsin-Chuan Chen, Jen-Shiun Chiang (2005)

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DOI: 10.1109/AINA.2005.238

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Hsin-Chuan Chen, Jen-Shiun Chiang:
Low-Power Way-Predicting Cache Using Valid-Bit Pre-Decision for Parallel Architectures. AINA 2005: 203-206

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