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"Implementing an efficient vector instruction set in a chip multi-processor ..."

Chris R. Jesshope (2001)

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DOI: 10.1109/ACAC.2001.903363

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Chris R. Jesshope:
Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines. ACSAC 2001: 80-88

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