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"A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and ..."

Takushi Hashida et al. (2014)

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DOI: 10.1109/VLSIC.2014.6858359

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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  - conf/vlsic/HashidaTOSSNTHS14
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  - https://dblp.org/rec/conf/vlsic/HashidaTOSSNTHS14
Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura:
A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution. VLSIC 2014: 1-2

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