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Matteo Monchiero
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2020 – today
- 2023
- [i3]Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn:
RETROSPECTIVE: Corona: System Implications of Emerging Nanophotonic Technology. CoRR abs/2306.15688 (2023) - [i2]Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn:
Corona: System Implications of Emerging Nanophotonic Technology. CoRR abs/2307.06294 (2023)
2010 – 2019
- 2013
- [c24]Javier Carretero, Enric Herrero, Matteo Monchiero, Tanausú Ramírez, Xavier Vera:
Capturing vulnerability variations for register files. DATE 2013: 1468-1473 - 2011
- [c23]Jen-Cheng Huang, Matteo Monchiero, Yoshio Turner, Hsien-Hsin S. Lee:
Ally: OS-Transparent Packet Inspection Using Sequestered Cores. ANCS 2011: 1-11 - [c22]Javier Carretero, Xavier Vera, Jaume Abella
, Tanausú Ramírez, Matteo Monchiero, Antonio González
Hardware/software-based diagnosis of load-store queues using expandable activity logs. HPCA 2011: 321-331 - [p1]Jung Ho Ahn
CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study. Low Power Networks-on-Chip 2011: 223-254
2000 – 2009
- 2009
- [j8]Jacob Leverich, Matteo Monchiero, Vanish Talwar, Parthasarathy Ranganathan, Christos Kozyrakis:
Power Management of Datacenter Workloads Using Per-Core Power Gating. IEEE Comput. Archit. Lett. 8(2): 48-51 (2009) - [j7]Matteo Monchiero, Jung Ho Ahn, Ayose Falcón, Daniel Ortega, Paolo Faraboschi:
How to simulate 1000 cores. SIGARCH Comput. Archit. News 37(2): 10-19 (2009) - [j6]Eduardo Argollo, Ayose Falcón, Paolo Faraboschi
COTSon: infrastructure for full system simulation. ACM SIGOPS Oper. Syst. Rev. 43(1): 52-61 (2009) - [c21]Antonino Tumeo
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform. ASP-DAC 2009: 317-322 - [c20]Matteo Monchiero, Ramon Canal, Antonio González
Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs. ICPP 2009: 1-8 - [c19]Antonino Tumeo
A multiprocessor self-reconfigurable JPEG2000 encoder. IPDPS 2009: 1-8 - 2008
- [j5]Matteo Monchiero, Ramon Canal, Antonio González
Power/Performance/Thermal Design-Space Exploration for Multicore Architectures. IEEE Trans. Parallel Distributed Syst. 19(5): 666-681 (2008) - [c18]Antonino Tumeo
Lightweight DMA management mechanisms for multiprocessors on FPGA. ASAP 2008: 275-280 - [c17]Antonino Tumeo
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications. DATE 2008: 1039-1044 - [c16]Matteo Monchiero, Gianluca Palermo
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level. DSD 2008: 158-164 - [c15]Shyamkumar Thoziyoor, Jung Ho Ahn
A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies. ISCA 2008: 51-62 - [c14]Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino
Corona: System Implications of Emerging Nanophotonic Technology. ISCA 2008: 153-164 - 2007
- [j4]Matteo Monchiero, Gianluca Palermo
Exploration of distributed shared memory architectures for NoC-based multiprocessors. J. Syst. Archit. 53(10): 719-732 (2007) - [c13]Antonino Tumeo
A Self-Reconfigurable Implementation of the JPEG Encoder. ASAP 2007: 24-29 - [c12]Antonino Tumeo
A design kit for a fully working shared memory multiprocessor on FPGA. ACM Great Lakes Symposium on VLSI 2007: 219-222 - [c11]Antonino Tumeo, Matteo Monchiero, Gianluca Palermo
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs. ISVLSI 2007: 331-336 - [c10]Antonino Tumeo
An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb. ISVLSI 2007: 449-450 - [c9]Antonino Tumeo
An Interrupt Controller for FPGA-based Multiprocessors. ICSAMOS 2007: 82-87 - [i1]Oreste Villa, Patrick Schaumont, Ingrid Verbauwhede, Matteo Monchiero, Gianluca Palermo:
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip. CoRR abs/0710.4646 (2007) - 2006
- [j3]Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa:
An efficient synchronization technique for multiprocessor systems on-chip. SIGARCH Comput. Archit. News 34(1): 33-40 (2006) - [j2]Matteo Monchiero, Gianluca Palermo
Efficient Synchronization for Embedded On-Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 14(10): 1049-1062 (2006) - [c8]Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa:
Power/performance hardware optimization for synchronization intensive applications in MPSoCs. DATE 2006: 606-611 - [c7]Matteo Monchiero, Ramon Canal, Antonio González
Design space exploration for multicore architectures: a power/performance/thermal view. ICS 2006: 177-186 - [c6]Simone Borgio, Davide Bosisio, Fabrizio Ferrandi
Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA. ICSAMOS 2006: 107-114 - [c5]Matteo Monchiero, Gianluca Palermo
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors. ICSAMOS 2006: 144-151 - 2005
- [j1]Matteo Monchiero, Gianluca Palermo
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach. Integr. 38(3): 515-524 (2005) - [c4]Oreste Villa, Patrick Schaumont
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip. DATE 2005: 804-805 - [c3]Matteo Monchiero, Gianluca Palermo:
The Combined Perceptron Branch Predictor. Euro-Par 2005: 487-496 - [c2]Guido Bertoni
AES Power Attack Based on Induced Cache Miss and Countermeasure. ITCC (1) 2005: 586-591 - 2004
- [c1]Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon:
Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors. ACM Great Lakes Symposium on VLSI 2004: 440-443
Coauthor Index
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