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Alejandro Millán 0001
Person information
- affiliation: University of Seville, Spain
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2020 – today
- 2020
- [j9]David Guerrero Martos
, Alejandro Millán Calderón, Jorge Juan-Chico, Julian Viejo
Using the complement of the cosine to compute trigonometric functions. EURASIP J. Adv. Signal Process. 2020(1): 1-21 (2020) - [j8]David Guerrero Martos, German Cano-Quiveu
Address-encoded byte order. Microprocess. Microsystems 78: 103268 (2020)
2010 – 2019
- 2016
- [j7]Juan Quiros, Sergey Verlan, Julian Viejo, Alejandro Millán, Manuel J. Bellido:
Fast Hardware Implementations of Static P Systems. Comput. Informatics 35(3): 687-718 (2016) - 2012
- [j6]Julian Viejo
Long-term on-chip verification of systems with logical events scattered in time. Microprocess. Microsystems 36(5): 402-408 (2012) - 2011
- [j5]David Guerrero Martos, Alejandro Millán
Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. J. Low Power Electron. 7(3): 444-452 (2011) - [j4]Julian Viejo
Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation. IEEE Trans. Instrum. Meas. 60(12): 3961-3963 (2011) - 2010
- [j3]Alejandro Millán
Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies. J. Low Power Electron. 6(1): 93-102 (2010) - [c12]Julian Viejo
Design and implementation of a suitable core for on-chip long-term verification. SIES 2010: 234-237
2000 – 2009
- 2008
- [c11]Alejandro Millán
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. PATMOS 2008: 389-398 - 2007
- [j2]David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa
Improving the Performance of Static CMOS Gates by Using Independent Bodies. J. Low Power Electron. 3(1): 70-77 (2007) - [c10]David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa
Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS 2007: 404-412 - [c9]Julian Viejo
Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES 2007: 337-340 - 2006
- [j1]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero Martos, Enrique Ostúa
Accurate Logic-Level Current Estimation for Digital CMOS Circuits. J. Low Power Electron. 2(1): 87-94 (2006) - [c8]Julian Viejo
Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements. IES 2006: 1-7 - 2005
- [c7]Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. PATMOS 2005: 337-347 - [c6]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa
Logic-Level Fast Current Simulation for Digital CMOS Circuits. PATMOS 2005: 425-435 - 2004
- [c5]Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa
Signal Sampling Based Transition Modeling for Digital Gates Characterization. PATMOS 2004: 829-837 - 2003
- [c4]Alejandro Millán, Manuel J. Bellido
Internode: Internal Node Logic Computational Model. Annual Simulation Symposium 2003: 241-248 - [c3]David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán:
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS 2003: 501-510 - 2002
- [c2]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. PATMOS 2002: 400-408 - [c1]Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). PATMOS 2002: 477-486
Coauthor Index
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