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M. Haykel Ben Jamaa
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2010 – 2019
- 2016
- [j3]Perceval Coudrain
, Papa Momar Souare, Rafael Prieto, Vincent Fiori, Alexis Farcy, Laurent Le Pailleur, Jean-Philippe Colonna, Cristiano Santos, Pascal Vivet
Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits. IEEE Des. Test 33(3): 21-36 (2016) - 2014
- [c22]Cristiano Santos, Papa Momar Souare, François de Crecy, Perceval Coudrain
Using TSVs for thermal mitigation in 3D circuits: Wish and truth. 3DIC 2014: 1-8 - 2013
- [c21]Papa Momar Souare, François de Crecy, Vincent Fiori, M. Haykel Ben Jamaa, Alexis Farcy, Sébastien Gallois-Garreignot, Andras Borbely, Jean-Philippe Colonna, Perceval Coudrain
Thermal correlation between measurements and FEM simulations in 3D ICs. 3DIC 2013: 1-6 - 2011
- [b1]M. Haykel Ben Jamaa:
Regular Nanofabrics in Emerging Technologies - Design and Fabrication Methods for Nanoscale Digital Circuits. Lecture Notes in Electrical Engineering 82, Springer 2011, ISBN 978-94-007-0649-1, pp. 1-188 [contents] - [j2]M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli:
An Efficient Gate Library for Ambipolar CNTFET Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 242-255 (2011) - [c20]Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Paul-Henry Morel, Jean-Philippe Noël, Fabien Clermidy, Ian O'Connor
Can we go towards true 3-D architectures? DAC 2011: 282-283 - [c19]Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy, Ian O'Connor
Evaluation of a crossbar multiplexer in a lithography-based nanowire technology. ISCAS 2011: 2930-2933 - [c18]Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy, Ian O'Connor
Ultra-fine grain FPGAs: A granularity study. NANOARCH 2011: 9-15 - 2010
- [c17]M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli:
Power consumption of logic circuits in ambipolar carbon nanotube technology. DATE 2010: 303-306 - [c16]Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Marina Reyboz, Giovanni Beneventi
Phase-change-memory-based storage elements for configurable logic. FPT 2010: 17-20 - [c15]Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Giovanni Betti Beneventi
Emerging memory technologies for reconfigurable routing in FPGA architecture. ICECS 2010: 62-65 - [c14]Ian O'Connor
Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics. ICECS 2010: 66-69 - [c13]Michele De Marchi, Shashikanth Bobba, M. Haykel Ben Jamaa, Giovanni De Micheli:
Synthesis of regular computational fabrics with ambipolar CNTFET technology. ICECS 2010: 70-73 - [c12]Davide Sacchetto, M. Haykel Ben Jamaa, Sandro Carrara, Giovanni De Micheli, Yusuf Leblebici:
Memristive devices fabricated with silicon nanowire schottky barrier transistors. ISCAS 2010: 9-12 - [c11]Nikolaos Archontas, Julius Georgiou
Characterization of memristive Poly-Si Nanowires via empirical physical modelling. ISCAS 2010: 1675-1678 - [c10]Davide Sacchetto, M. Haykel Ben Jamaa, Giovanni De Micheli, Yusuf Leblebici:
Design aspects of carry lookahead adders with vertically-stacked nanowire transistors. ISCAS 2010: 1715-1718 - [c9]Kotb Jabeur, David Navarro, Ian O'Connor
Reducing transistor count in clocked standard cells with ambipolar double-gate FETs. NANOARCH 2010: 47-52 - [c8]Michele De Marchi, M. Haykel Ben Jamaa, Giovanni De Micheli:
Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications. NANOARCH 2010: 65-70
2000 – 2009
- 2009
- [c7]M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli:
A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories. ASP-DAC 2009: 835-840 - [c6]M. Haykel Ben Jamaa, Gianfranco Cerofolini, Yusuf Leblebici, Giovanni De Micheli:
Complete nanowire crossbar framework optimized for the multi-spacer patterning technique. CASES 2009: 11-16 - [c5]M. Haykel Ben Jamaa, Yusuf Leblebici, Giovanni De Micheli:
Decoding nanowire arrays fabricated with the multi-spacer patterning technique. DAC 2009: 77-82 - [c4]M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli:
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis. DATE 2009: 622-627 - 2008
- [j1]M. Haykel Ben Jamaa, Kirsten E. Moselund
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 2053-2067 (2008) - [c3]M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli:
Programmable logic circuits based on ambipolar CNFET. DAC 2008: 339-340 - 2007
- [c2]Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini
Interactive presentation: Improving the fault tolerance of nanometric PLA designs. DATE 2007: 570-575 - [c1]M. Haykel Ben Jamaa, Kirsten E. Moselund
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. ICCAD 2007: 765-772
Coauthor Index
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