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Hiromitsu Kimura
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2010 – 2019
- 2018
- [j7]Motofumi Nakanishi, Shintaro Izumi, Mio Tsukahara, Hiroshi Kawaguchi
, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto:
A 11.3-µA Physical Activity Monitoring System Using Acceleration and Heart Rate. IEICE Trans. Electron. 101-C(4): 233-242 (2018) - 2017
- [c14]Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi
A 19-μA metabolic equivalents monitoring SoC using adaptive sampling. ASP-DAC 2017: 37-38 - 2016
- [c13]Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi
A 15-μA metabolic equivalents monitoring system using adaptive acceleration sampling and normally off computing. ICECS 2016: 61-64 - 2015
- [j6]Shintaro Izumi, Ken Yamashita, Masanao Nakano, Shusuke Yoshimoto, Tomoki Nakagawa, Yozaburo Nakai, Hiroshi Kawaguchi
Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector. IEEE Trans. Biomed. Circuits Syst. 9(5): 641-651 (2015) - [j5]Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi
A Wearable Healthcare System With a 13.7 µ A Noise Tolerant ECG Processor. IEEE Trans. Biomed. Circuits Syst. 9(5): 733-742 (2015) - [c12]Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi
A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques. ISCAS 2015: 2904-2907 - [c11]Shintaro Izumi, Hiroshi Kawaguchi
A ferroelectric-based non-volatile flip-flop for wearable healthcare systems. NVMTS 2015: 1-4 - 2014
- [j4]Hiromitsu Kimura, Zhiyong Zhong, Yuta Mizuochi, Norihiro Kinouchi, Yoshinobu Ichida, Yoshikazu Fujimori:
Highly Reliable Non-volatile Logic Circuit Technology and Its Application. IEICE Trans. Inf. Syst. 97-D(9): 2226-2233 (2014) - [c10]Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori, Shintaro Izumi, Hiroshi Kawaguchi
A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability. A-SSCC 2014: 21-24 - [c9]Shintaro Izumi, Ken Yamashita, Masanao Nakano, Tomoki Nakagawa, Yuki Kitahara, Koji Yanagida, Shusuke Yoshimoto, Hiroshi Kawaguchi
A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems. BioCAS 2014: 280-283 - 2013
- [c8]Shintaro Izumi, Ken Yamashita, Masanao Nakano, Toshihiro Konishi, Hiroshi Kawaguchi
A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system. ESSCIRC 2013: 145-148 - [c7]Hiromitsu Kimura, Zhiyong Zhong, Yuta Mizuochi, Norihiro Kinouchi, Yoshinobu Ichida, Yoshikazu Fujimori:
Highly Reliable Non-Volatile Logic Circuit Technology and Its Application. ISMVL 2013: 212-218 - [c6]Ken Yamashita, Shintaro Izumi, Masanao Nakano, Takahide Fujii, Toshihiro Konishi, Hiroshi Kawaguchi
A 38 μA wearable biosignal monitoring system with near field communication. NEWCAS 2013: 1-4
2000 – 2009
- 2007
- [c5]Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, Takashi Nakamura, Hidemi Takasu:
Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic. ASP-DAC 2007: 116-117 - 2005
- [j3]Akira Mochizuki, Hiromitsu Kimura, Mitsuru Ibuki, Takahiro Hanyu:
TMR-Based Logic-in-Memory Circuit for Low-Power VLSI. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(6): 1408-1415 (2005) - 2004
- [j2]Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu:
Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI. IEEE J. Solid State Circuits 39(6): 919-926 (2004) - [c4]Hiromitsu Kimura, Kostas Pagiamtzis
A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices. ISMVL 2004: 340-345 - 2003
- [j1]Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama:
Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and its Applications. J. Multiple Valued Log. Soft Comput. 9(1): 23-42 (2003) - 2002
- [c3]Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama:
Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. ISMVL 2002: 161-167 - 2000
- [c2]Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama:
DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. ISMVL 2000: 423-429
1990 – 1999
- 1999
- [c1]Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama:
Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. ISMVL 1999: 30-35
Coauthor Index
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